Clock-Embedded Data Packet Encoding for Display Signal Transmission

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Solution Overview

Problem

High-resolution display devices face challenges in efficiently transmitting image data signals and data control signals due to increased run length during clock data recovery, leading to increased data processing overhead.

Innovation Solution

A display device with a data generator and controller that encodes and decodes clock-embedded data packets, reducing maximum run length by structuring packets with headers and symbols containing address information, allowing for efficient clock recovery without additional toggle bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If redundant bits are inserted into data to reduce run length for clock data recovery, then clock recovery reliability is improved, but data processing overhead increases

Engineering Contradiction:
Improveclock recovery reliabilityVSAvoiddata processing overhead
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The data stream is segmented into data packets, each containing a header with address information and a payload. This segmentation allows the system to track data positions without requiring redundant toggle bits, as the header information provides sufficient context for clock data recovery while maintaining efficient data processing

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Address information is preliminarily embedded in the packet headers before data transmission. This preliminary encoding of position information eliminates the need for run-length control through redundant bits during transmission, as the receiver can use the pre-encoded address information to synchronize and recover the clock signal efficiently

Inventive Principle:
Principle #10Preliminary action

2Manufacturing precision

If high resolution display is implemented, then image quality is improved, but run length in data transmission increases

Engineering Contradiction:
Improvedisplay resolutionVSAvoidrun length
Core Design Contradiction:
Manufacturing precisionVSLength of moving object

Solution Approach 1:

The patent transitions from time-domain run-length control to spatial-domain address encoding by organizing data into packets with headers containing address information. This dimensional shift allows high-resolution data to be transmitted efficiently without being constrained by run-length limitations, as the address information provides positional context independent of data sequence length

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS10170033B2Display device
Publication Date: 2019.01.01 SAMSUNG ELECTRONICS CO LTD
  • US10170033B2 patent drawing
  • US10170033B2 patent drawing
  • US10170033B2 patent drawing

AI summary

A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.