Clock Embedded Data Signal Transmission for Display Apparatus
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Solution Overview
Problem
Display apparatuses face challenges in transmitting high-resolution and high-frame-rate data due to increased electromagnetic interference (EMI) and the need for additional lines for clock signals, which also increases the area of printed circuit boards (PCBs) and complexity.
Innovation Solution
A method that divides data into 3-bit units, generates first and second clock embedded data signals, and a third data signal, where the clock signal is embedded within the first and second bits, allowing for transmission without a separate clock line, using pulse-amplitude-modulation to differentiate bit values and restore the clock signal at the receiver.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmitting speed is increased to achieve high resolution and high frame rate, then productivity is improved, but the number of lines increases and device complexity worsens
Solution Approach 1:
The patent combines the clock signal and data signals into a single integrated signal for transmission. The transmitter generates a composite signal that embeds both clock and data information, which is then transmitted through one shared line rather than requiring separate lines for clock and data, thereby reducing the total number of lines while maintaining high data transmission speed
Solution Approach 2:
The transmitted signal serves multiple functions simultaneously: it carries both clock synchronization information and data information. The receiver can extract both the clock signal and data from this single composite signal, making the transmission line universal and multi-functional, thus reducing the number of lines required
2Reliability
If an additional clock line is added to transmit clock signal, then reliability is improved, but electromagnetic interference increases and device complexity worsens
Solution Approach 1:
The patent merges the clock signal transmission with data signal transmission by embedding the clock signal within the data transmission channel. This eliminates the need for a separate clock line, thereby reducing electromagnetic interference between adjacent lines while maintaining reliable clock signal delivery through the embedded clock mechanism
Solution Approach 2:
The composite signal acts as an intermediary that carries both clock and data information. By using this intermediate signal form, the system avoids direct parallel transmission of separate clock and data lines, thereby reducing electromagnetic interference while still providing reliable clock synchronization through the embedded clock components
3Productivity
If the number of lines is increased to transmit high resolution data, then productivity is improved, but area of printed circuit board increases
Solution Approach 1:
The patent combines multiple signal functions into fewer physical lines. By integrating clock and data transmission into a unified signal structure that uses fewer lines, the overall trace routing area on the PCB is reduced while maintaining the capability to transmit high-resolution data at high frame rates
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances data transmission speed, reduces the number of lines required, minimizes PCB area, and decreases electromagnetic interference, enabling efficient high-resolution and high-frame-rate data transmission without the need for additional clock lines.
Implementation Method 1
generating the first and second clock embedded data signals and the third data signal may include, pulse-amplitude-modulating the first and second bits of the units to generate first and second signals, respectively
Implementation Method 2
reversing polarities of the first and second signals in response to the clock signal and embedding the clock signal in the first and second signals where the polarity reversal occurs
Implementation Method 3
restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals
Data Source
AI summary
A method of processing data including dividing, at a transmitter, data into 3-bit units, generating, at the transmitter, first and second clock embedded data signals and a third data signal, wherein a clock signal and first bits of the units are included in the first clock embedded data signal, the clock signal and second bits of the units are included in the second clock embedded data signal and third bits of the units are included in the third data signal, transmitting, from the transmitter to a receiver, the first and second clock embedded data signals and the third data signal, and restoring, at the receiver, the first and second bits and the clock signal from the first and second clock embedded data signals and the third bits from the third data signal.