Clock-Embedded Serial Communication Using Polarity-Inverted PAM Signals
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Solution Overview
Problem
Conventional serial communication methods using separate clock channels for high-definition video transmission suffer from electromagnetic interference and incur a 2-bit overhead due to embedding clock information in the data stream, which is inefficient.
Innovation Solution
The method embeds clock information in a data stream by inverting the polarities of odd-numbered and even-numbered data signals and transmitting them as 4-level pulse amplitude modulated signals, eliminating the need for a dedicated clock channel and reducing bit overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate wiring for clock channel is used, then clock information can be transmitted reliably, but electromagnetic interference increases
Solution Approach 1:
The patent combines the clock channel and data channel into a single integrated transmission channel. Clock information is embedded within the data stream using polarity inversion techniques, eliminating the need for separate clock wiring and thereby reducing electromagnetic interference while maintaining reliable clock transmission.
Solution Approach 2:
The data transmission channel is designed to serve dual purposes: transmitting both data information and clock synchronization information simultaneously. This multi-functionality is achieved through encoding techniques where polarity changes in the data stream convey clock timing, allowing one channel to perform multiple functions.
2Device complexity
If clock information is embedded in data stream using 8B/10B coding, then dedicated clock channel is eliminated, but 2-bit overhead is incurred
Solution Approach 1:
Instead of adding extra bits for clock information (conventional approach), the patent inverts the approach by using the existing data bits themselves to carry clock information. The polarity of data signals is inverted at clock transitions, allowing clock timing to be extracted from the data stream without requiring additional overhead bits.
Solution Approach 2:
The patent changes the parameter used for clock encoding from bit count (8B/10B adds 2 bits per 8 bits) to signal polarity. By modulating the polarity of existing data signals according to clock timing, the system embeds clock information without increasing the number of bits transmitted, thereby eliminating the 2-bit overhead problem.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces electromagnetic interference and eliminates the 2-bit overhead, enabling efficient serial communication by embedding clock information directly in the data stream without increasing bit overhead.
Implementation Method 1
a first signal generator for generating the odd-numbered embedded clock signal; and a second signal generator for generating the even-numbered embedded clock signal, wherein the first and second signal generators pulse amplitude modulate the odd-numbered and even-numbered data streams to have amplitudes having different polarities, respectively
Data Source
AI summary
Apparatus for serial communication using embedded clock signals includes a data divider for dividing a data stream into odd-numbered and even-numbered data streams; a clock-embedded signal generator for generating odd-numbered and even-numbered embedded clock signals by pulse amplitude modulating the odd-numbered and even-numbered data streams and, when an external clock is input, inverting polarities of the pulse amplitude modulated odd-numbered and even-numbered data streams; a clock-embedded signal recovery unit for recovering the odd-numbered and even-numbered data streams by comparing amplitudes of the odd-numbered and even-numbered embedded clock signals with reference voltages, respectively, and recovering synchronization information of the clock by detecting when amplitude polarities of the odd-numbered and even-numbered embedded clock signals are inverted; and a data integrator for integrating the odd-numbered and even-numbered data streams and supplying the result as the data stream.