Clock Embedded Multi-Level Signaling for Display Interfaces
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional intra-panel interfaces for Flat Panel Displays (FPDs) face issues with electromagnetic interference (EMI), signal distortion, and high-speed data transmission challenges due to multi-drop methods, which limit operating speed and increase manufacturing costs.
Innovation Solution
A novel intra-panel interface that embeds a clock signal within the data signal using multi-level signaling, reducing the number of signal lines and EMI, and enabling accurate sampling by separating the clock signal from the data signal using magnitude differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a separate clock signal line is used to synchronize data transmission, then data sampling accuracy is improved, but the number of signal lines increases and EMI is generated
Solution Approach 1:
The patent combines the clock signal and data signal into a single signal line by encoding the clock information within the data signal itself. The transmitter encodes both clock and data information in one signal, which is then transmitted through a single line to the receiver, eliminating the need for separate clock and data lines while maintaining synchronization accuracy.
Solution Approach 2:
The single signal line serves multiple functions simultaneously: it transmits both clock synchronization information and data information. The encoded signal contains embedded clock ticks that enable the receiver to synchronize data sampling while also carrying the actual data payload, making the signal line universal for both timing and data transmission.
2Device complexity
If a multi-drop method is used to share clock signals among multiple column driver ICs, then the number of clock lines is reduced, but operating speed is limited due to signal load
Solution Approach 1:
The patent segments the clock signal transmission by embedding individual clock ticks within each data packet sent to specific column driver ICs. Instead of broadcasting a shared clock signal that must be distributed to multiple devices (multi-drop), each receiver gets its own synchronized clock information embedded in its dedicated data stream, enabling higher operating speeds without the limitations of signal loading in shared lines.
3Speed
If separate clock lines are connected to each column driver IC using point-to-point method, then operating speed is improved, but signal line overhead and manufacturing cost increase
Solution Approach 1:
The patent merges the clock signal and data signal into a single transmission channel. By encoding the clock information within the data signal itself, the system achieves point-to-point synchronization performance without requiring separate physical clock lines for each column driver IC, thereby reducing signal line overhead and manufacturing costs while maintaining high operating speeds.
4Object-affected harmful factors
If conventional differential signaling methods are used, then EMI is reduced compared to single-ended signaling, but impedance mismatch at line split points causes signal distortion
Solution Approach 1:
The patent extracts the clock signal from the data transmission path and embeds it within the data signal itself. By eliminating the need to split clock signals at intermediate points (which causes impedance mismatch and signal distortion in conventional multi-drop differential signaling), the system maintains signal integrity while still using differential signaling to reduce EMI. The embedded clock approach removes the problematic line split points entirely.
Data Source
AI summary
The present invention relates to a display, a timing controller and a column driver IC, and more particularly to a display, timing controller and column driver integrated circuit using clock embedded multi-level signaling. The present invention provides a timing controller including a transmitter for transmitting a transmission signal wherein a transmission clock signal is embedded therein between a transmission data signal to have a signal magnitude different from that of the transmission data signal. The present invention also provides a column driver integrated circuit including a receiving unit for separating a clock signal from a received signal using a magnitude of the received signal, and for performing a sampling of a received data signal from the received signal using the separated clock signal.