Clock-Embedded Transceiver Error Detection for MIPI Display Links
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Solution Overview
Problem
The use of a clock line in MIPI protocol-based communication between a display device and a processor increases physical and spatial costs and power consumption, and existing clock-embedded data schemes face challenges in handling clock embedding-related errors.
Innovation Solution
A transceiver system that transmits clock-embedded data through a data line, including a clock training pattern, start pattern, and end pattern, with a receiver detecting and outputting error flags for clock embedding-related errors such as loss-of-lock, initialization, start pattern, and end pattern errors, which are not defined in MIPI D-PHY & DSI standards, and allows for selective masking and adjustment of error flags.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a clock line is used for MIPI protocol communication, then clock signal transmission is reliable, but physical cost and power consumption increase
Solution Approach 1:
The patent merges the clock signal and data signal into a single data line by embedding clock information within the data stream. The transmitter encodes clock signals along with data, and the receiver extracts both, eliminating the need for a separate clock line while maintaining synchronization and reducing power consumption.
Solution Approach 2:
The data line is given multi-functionality by enabling it to carry both data transmission and clock signal functions simultaneously. This universal usage of the data line for dual purposes removes the requirement for a dedicated clock line, thereby reducing physical cost and power consumption.
2Reliability
If a clock line is used for MIPI protocol communication, then clock signal transmission is reliable, but physical cost increases
Solution Approach 1:
The patent merges the clock signal and data signal into a single data line by embedding clock information within the data stream. The transmitter encodes clock signals along with data, and the receiver extracts both, eliminating the need for a separate clock line while maintaining synchronization and reducing power consumption.
Solution Approach 2:
The data line is given multi-functionality by enabling it to carry both data transmission and clock signal functions simultaneously. This universal usage of the data line for dual purposes removes the requirement for a dedicated clock line, thereby reducing physical cost and power consumption.
3Use of energy by moving object
If clock-embedded data scheme is used, then physical cost and power consumption are reduced, but clock embedding-related error handling capability is insufficient
Solution Approach 1:
The patent implements feedback mechanisms where the receiver detects clock embedding-related errors and sends error flags back to the transmitter. The transmitter receives these error flags and adjusts its transmission accordingly, creating a closed-loop error handling system that improves reliability while maintaining the power-saving benefits of clock embedding.
Solution Approach 2:
The patent incorporates error detection and correction mechanisms in advance within the clock-embedded data transmission process. By preparing error handling capabilities beforehand through embedded error detection codes and feedback pathways, the system can quickly respond to errors without compromising the overall reliability.
Data Source
AI summary
A transceiver includes a transmitter which transmits clock-embedded data through a line, where the clock-embedded data includes a clock training pattern, a start pattern, an encoded payload, and an end pattern, and a receiver which receives the clock-embedded data through the line, detects a clock embedding-related error from the clock-embedded data, and outputs an error flag corresponding to the clock embedding-related error to the transmitter.