Integrated Clock Enable Latch for Glitch-Free Pulse Control
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Solution Overview
Problem
Existing clock control circuits face challenges in seamlessly transitioning from full duty-cycle clocks to pulsed clocks due to the need for logical inversion of enable signals and the addition of extra control circuits, which complicates the design and increases area and timing constraints.
Innovation Solution
A configurable integrated pulse-control and enable latch circuit that can operate in both clock and pulse modes without requiring logical state changes in the enable signals, using a tri-state inverter and storage element to generate control signals that either enable or control the length of clock pulses, allowing for easy conversion between full duty-cycle and pulsed clock signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate clock enable control latch and clock pulse control circuit are used, then clock signal can be controlled, but device complexity increases
Solution Approach 1:
The patent combines the clock enable control latch and clock pulse control circuit into a single integrated circuit. The enable input controls both the enable signal generation and pulse width control functions within one unified structure, eliminating the need for separate circuits while maintaining full control capabilities.
Solution Approach 2:
The integrated circuit performs multiple functions: it generates enable signals to control clock propagation, adjusts pulse widths by controlling the duration of the enable signal, and prevents glitches by ensuring proper timing. A single circuit structure handles all these diverse control functions that previously required separate dedicated circuits.
2Duration of action of moving object
If additional clock pulse control circuit is added, then pulse length can be controlled, but area constraints are increased
Solution Approach 1:
The enable control latch and pulse width control functionality are merged into one compact circuit. The same enable signal path that controls clock propagation also controls pulse duration, eliminating the need for additional separate pulse control circuitry that would occupy extra area.
Solution Approach 2:
The integrated circuit uses the enable signal to simultaneously control both the presence and duration of clock pulses. This multi-functional approach allows pulse length control without requiring dedicated pulse width control circuitry, thereby saving chip area.
3Productivity
If clock enable signal transitions at incorrect time, then clock output can be generated, but glitches occur
Solution Approach 1:
The circuit ensures the enable signal is properly established and stable before allowing clock propagation. The latch structure captures the enable state at the appropriate time and maintains it throughout the clock pulse duration, preventing mid-pulse transitions that would cause glitches.
Solution Approach 2:
The clocked latch structure provides feedback to maintain the enable signal state throughout the clock high phase. This feedback mechanism ensures the enable signal remains stable during the entire pulse duration, preventing incorrect transitions that would generate glitches in the clock output.
Data Source
AI summary
The described embodiments provide a configurable clock circuit. The clock circuit includes a control and enable circuit and a clock distribution circuit. During operation, when a signal on an enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a clock mode, the control and enable circuit generates an enable signal on a control output to enable a signal on a clock input to propagate through the clock distribution circuit to the clock output. Alternatively, when a signal on the enable input to the control and enable circuit is asserted and the control and enable circuit is configured in a pulse mode, the control and enable circuit generates a pulsed control signal on the control output to control a length of a pulse generated from the clock input on a clock output by the clock distribution circuit.