Clock Enable Circuit That Stops Unneeded Internal Clock Toggling
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Solution Overview
Problem
Conventional clock enabler circuits consume power unnecessarily due to internal circuit operation with every clock signal toggle, regardless of the clock enable signal value.
Innovation Solution
A clock enabler circuit with a state holding unit, clock signal output unit, and control unit that manages the output clock signal based on the clock enable signal, stopping unnecessary toggling of the internal clock signal and reducing power consumption by controlling the clock signal operation according to the enable state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the clock signal is continuously toggled to maintain circuit operation, then the circuit can respond to clock events, but power consumption increases due to unnecessary operations when the clock enable signal is inactive
Solution Approach 1:
The patent applies dynamics by making the internal clock signal's operational state changeable based on the clock enable signal. When the clock enable signal is active, the internal clock signal toggles to maintain circuit operation. When the clock enable signal is inactive, the internal clock signal stops toggling to reduce power consumption. This dynamic adjustment of the clock signal's operational state resolves the contradiction between maintaining reliability and reducing power consumption.
Solution Approach 2:
The patent changes the operational parameter of the internal clock signal based on the clock enable signal state. By controlling whether the internal clock signal toggles or remains static, the circuit dynamically adjusts its operational parameters to balance between maintaining circuit functionality and reducing power consumption during inactive periods.
2Ease of operation
If the internal clock signal continues to toggle regardless of the clock enable signal value, then the circuit maintains readiness to respond, but unnecessary circuit operations occur consuming additional power
Solution Approach 1:
The patent makes the internal clock signal's toggling behavior dynamic based on the clock enable signal. When the clock enable signal indicates an enable state, the internal clock signal toggles to maintain circuit readiness. When the clock enable signal indicates a disable state, the internal clock signal stops toggling to eliminate unnecessary operations and reduce energy loss.
Solution Approach 2:
The patent extracts the unnecessary clock toggling operations by conditionally disabling the internal clock signal when the clock enable signal is inactive. This separation of operational and non-operational states removes the harmful energy consumption from unnecessary operations while preserving the ability to quickly resume operation when needed.
Data Source
AI summary
An unnecessary circuit operation in a clock enabler circuit accompanying toggling of a clock signal is suppressed. A state holding unit performs a holding operation of a state as to whether or not to output an output clock signal according to an internal clock signal. A clock signal output unit controls output of the output clock signal according to the state held in the state holding unit. A control unit supplies, to the state holding unit, the internal clock signal and a value of the state that are necessary for the holding operation in the state holding unit on a basis of a clock signal and a clock enable signal from an outside.