Clock-Error Estimation for Two-Clock UWB Devices
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Solution Overview
Problem
Two-clock electronic devices, particularly in UWB location systems, face challenges in accurately estimating clock-errors within short periods, leading to inefficiencies in power consumption and synchronization, especially during transitions between high and low power modes.
Innovation Solution
A method for deriving an estimation value of clock-error by comparing the actual and nominal periods of slave and master clocks, using a measurement time period that includes a common multiple of both clock periods, allowing for precise calibration and optimization of sleep modes and wake-up times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the device operates the high frequency clock continuously to maintain accurate timing, then the synchronization accuracy is improved, but the power consumption increases
Solution Approach 1:
The patent implements periodic clock-error estimation at specific time intervals rather than continuously. The device switches between high frequency clock (for accurate timing during location updates) and low power clock (for power saving during idle periods), performing clock-error estimation periodically to maintain synchronization accuracy while reducing overall power consumption.
2Use of energy by moving object
If the device uses the low power clock for extended periods to save energy, then the power consumption is reduced, but the clock-error estimation accuracy deteriorates
Solution Approach 1:
The patent performs clock-error estimation in advance during brief high frequency clock operation periods, before transitioning to low power mode. By estimating the clock-error while the high frequency clock is still synchronized, the device can then use the low power clock for extended periods without significantly degrading timing accuracy, thus saving power while maintaining adequate estimation precision.
3Measurement precision
If the device performs frequent clock-error estimations to maintain precision, then the timing accuracy is improved, but the productivity decreases due to more frequent wake-ups
Solution Approach 1:
The patent implements periodic clock-error estimation at optimized time intervals rather than frequently or continuously. This allows the device to maintain adequate timing accuracy while minimizing the number of wake-up events from sleep mode, thereby improving overall operation efficiency and productivity.
4Measurement precision
If the device extends the measurement time period to improve estimation accuracy, then the clock-error precision is improved, but the time required for measurement increases
Solution Approach 1:
The patent performs clock-error estimation in advance during brief high frequency clock operation periods, capturing timing data before transitioning to low power mode. This preliminary measurement approach achieves adequate estimation precision without requiring extended measurement time periods, thus minimizing the time the device must remain awake and operational.
Data Source
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AI summary
A method is disclosed for deriving an estimation value of a clock-error (E) for a slave clock (3), wherein the slave clock (3) is set at a nominal slave period (TLCLK_n) and outputs a sequence of slave clock signals (3') at an actual slave period (TLCLK) and wherein the difference between the actual slave period (TLCLK) and the nominal slave period (TLCLK_n) is approximated by the estimation value of the clock-error (E). The method includes: - receiving a sequence of master clock signals (5') at a master period (THCLK) that is output from a master clock (5), and a sequence of slave clock signals (3') at an actual slave period (TLCLK) that is output from the slave clock (3), - providing a measurement time period (43) that begins at a starting time point (43_s) and ends at an ending time point (43_e), wherein the measurement time period (43) includes a common multiple time period, the common multiple time period ends at the ending time point (43_e) and has a length in time that is a first multiple (n) of the nominal slave period (TLCLK_n) and is a second multiple (m) of the master period (THCLK), - providing a sequence of storing time points (43_i) temporally displaced within the common multiple time period by the actual slave period (TLCLK), the last of the storing time points being the ending time point (43_e) of the measurement time period (43), - starting to count the slave signals (3') and the master signals (5') at the starting time point (43_s), - for more than one storing time point (43_i), storing a master count value that represents the counted master signals (5') in association with the respective storing time point (43_i), - deriving an actual master count sum value by adding the stored master count values, - deriving, for the more than one storing time points, a nominal master count sum value, and - deriving the estimation of the clock-error (E) for the slave clock (3) by relating the actual master count sum value to the nominal count sum value.