Receiver Clock Estimation via Delta Carrier Phase Updating

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Current positioning methods in 5G wireless communication systems face challenges in accurately determining receiver clock values, especially when primary signals are lost, which affects the precision of position estimation and increases outlier detection errors.

Innovation Solution

The implementation of delta carrier phase updating and recursive filtering techniques to estimate receiver clock drift, allowing for precise determination of receiver clock values even in the absence of primary signals, using available positioning signals to update clock terms and maintain accurate position information.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If receiver clock value is determined using primary positioning signals, then positioning accuracy is improved, but system reliability deteriorates when primary signals are lost

Engineering Contradiction:
Improvepositioning accuracyVSAvoidsystem reliability
Core Design Contradiction:
Measurement precisionVSReliability

Solution Approach 1:

The patent introduces an intermediary clock drift estimation mechanism that mediates between the primary positioning signals and the receiver clock. When primary signals are lost, the clock drift estimator uses available positioning signals from alternative sources to maintain clock value determination, ensuring continuous positioning capability without complete dependency on primary signals.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent changes the parameter approach from direct clock value determination using primary signals to clock drift estimation using available signals. By estimating clock drift rates and applying them to maintain clock values, the system can adapt to signal availability changes and maintain positioning accuracy regardless of which specific signals are available.

Inventive Principle:
Principle #35Parameter changes

2Device complexity

If empirical models are used for clock estimation, then device complexity is reduced, but measurement precision deteriorates due to increased outlier detection errors

Engineering Contradiction:
Improvedevice complexityVSAvoidclock estimation precision
Core Design Contradiction:
Device complexityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where clock drift estimates are continuously refined using available positioning signals. The system monitors signal quality and adjusts the clock estimation process accordingly, providing feedback to improve precision while avoiding complete reliance on simple empirical models.

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent transitions from static empirical models to dynamic clock drift estimation. The system adaptively estimates clock drift rates in real-time based on actual signal conditions, allowing the estimation process to respond to changing environmental conditions and maintain high precision without fixed model limitations.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20240406928A1Precise positioning receiver clock estimation without primary signal dependency
Publication Date: 2024.12.05 QUALCOMM INC
  • US20240406928A1 patent drawing
  • US20240406928A1 patent drawing
  • US20240406928A1 patent drawing

AI summary

A positioning method includes: receiving, at an apparatus from a first signal source, a first positioning signal; determining, at the apparatus, a first receiver clock value with respect to the first positioning signal; determining, at the apparatus in response to loss of reception of the first positioning signal, a drift of the first receiver clock value using delta carrier phase updating based on one or more available positioning signals; and determining, at the apparatus, a second receiver clock value based on the first receiver clock value and the drift of the first receiver clock value.