Clock Circuit Exit Point Delay Grouping
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Solution Overview
Problem
Determining accurate delays for exit points in clock circuits of programmable integrated circuits is challenging due to the large number of circuit nodes and varying operating contexts, making it computationally infeasible to evaluate all possible combinations, which is essential for circuit design, simulation, and determining maximum operating frequency.
Innovation Solution
A method involving a processor to determine groups of contexts for exit points based on characteristics and types, forming sub-groups based on delay values, and calculating a delay value for each sub-group, allowing for reduced complexity and increased performance in electronic design automation systems.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all possible combinations of operating contexts for different circuit nodes are evaluated to achieve greater accuracy, then measurement precision of delay information is improved, but device complexity and computational feasibility deteriorate
Solution Approach 1:
The patent segments the large set of exit points into multiple groups based on shared characteristics (such as clock buffer type, wire type, and load type). Instead of evaluating all possible combinations of operating contexts for each individual exit point, the method evaluates contexts at the group level, significantly reducing computational complexity while maintaining acceptable accuracy for circuit design and simulation tasks.
Solution Approach 2:
The patent changes the parameter representation by introducing characteristic-based grouping parameters rather than evaluating individual exit point parameters. By defining groups with shared characteristics (clock buffer characteristics, wire characteristics, load characteristics), the method transforms the problem from evaluating numerous individual parameters to evaluating fewer group-level parameters, making the computation feasible.
2Reliability
If all possible combinations of operating contexts are evaluated to obtain accurate delay information, then reliability of circuit design is improved, but loss of time in computation increases
Solution Approach 1:
By segmenting exit points into characteristic-based groups, the patent reduces the number of delay evaluations required from potentially millions (if all individual exit points were evaluated separately) to a manageable number of group evaluations. This segmentation maintains reliability for circuit design decisions while dramatically reducing computation time.
Solution Approach 2:
The patent applies partial action by evaluating only the necessary group-level characteristics rather than all possible individual exit point combinations. This partial evaluation approach provides sufficient accuracy for circuit design and simulation without the excessive computational burden of complete enumeration, achieving an optimal balance between reliability and efficiency.
3Productivity
If the number of variables and memory required are reduced to process larger circuit designs, then productivity is improved, but measurement precision of delay values may deteriorate
Solution Approach 1:
The patent segments exit points into characteristic-based groups, reducing the number of variables from individual exit point delays to group-level delay representations. This segmentation enables processing of larger circuit designs with limited memory while maintaining sufficient delay precision for design decisions, as groups with similar characteristics share representative delay values.
Solution Approach 2:
The characteristic-based grouping creates universal representations that can be applied across multiple exit points sharing the same characteristics. A single group delay value serves multiple exit points, reducing memory requirements and enabling processing of larger designs while maintaining adequate precision through the universality of the characteristic-based classification system.
Data Source
AI summary
Generating delays for a clock circuit includes, determining, using a processor, groups of contexts for exit points of the clock circuit based upon a plurality of characteristics and a type selected from a plurality of different types for each characteristic, forming, using the processor, sub-groups of the exit points based upon delay values for the exit points, and determining, using the processor, a mean delay value for each sub-group.