Clock Fail Detection Using Ping-Pong Integrator Timing
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Solution Overview
Problem
Conventional clock fail detectors have a response time that is not adaptable to varying clock periods and is sensitive to process variations, leading to inaccuracies and poor performance in electronic devices.
Innovation Solution
A clock fail detector architecture that includes a timing control signal generator and multiple clock fail detection modules, utilizing first integrators, sample and hold circuits operating in ping pong mode, and a comparator to convert clock periods into reference and ramp signals for precise fail detection, reducing sensitivity to process variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional clock fail detector uses a constant response time, then the circuit structure is simple, but the response time cannot adapt to varying clock periods and is sensitive to process variations
Solution Approach 1:
The patent implements dynamic response time by using integrators that convert clock periods into voltage signals. The response time is dynamically adjusted based on the actual clock period duration, allowing the detector to adapt to varying clock speeds. The first integrator accumulates voltage over one clock period, and the second integrator accumulates over N clock periods, creating a response time that scales with the clock period rather than being fixed.
Solution Approach 2:
The patent changes the parameter of response time from a constant value to a variable that depends on the clock period. By using voltage integration proportional to time, the response time parameter becomes dynamically determined by the clock signal itself rather than being a fixed circuit constant, thereby achieving adaptability to process variations and different clock frequencies.
2Measurement precision
If a conventional clock fail detector has fixed response time, then manufacturing is easier, but measurement precision deteriorates due to sensitivity to process variations
Solution Approach 1:
The patent replaces traditional time-based measurement mechanisms with voltage integration. Instead of using complex timing circuits that are sensitive to process variations, the system converts time measurement into voltage accumulation through integrators. This substitution of the measurement mechanism improves precision by making the response time proportional to the actual clock period rather than dependent on fixed circuit constants that vary with manufacturing processes.
3Productivity
If the clock frequency increases, then productivity improves, but the fixed response time becomes too long relative to the clock period
Solution Approach 1:
The patent makes the response time dynamic and proportional to the clock period. When clock frequency increases, the clock period decreases, and consequently the response time automatically decreases. This is achieved through the integrator-based measurement where the response time is determined by the actual duration of clock periods rather than a fixed constant, allowing the system to maintain appropriate response timing across different operating frequencies.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves higher precision and optimal performance by ensuring the response time is not sensitive to process variations, allowing for accurate clock fail detection across different clock speeds.
Implementation Method 1
The multiple first integrators are arranged to convert multiple previous clock periods of the clock signal into multiple reference voltages
Implementation Method 2
the multiple sample and hold circuits may be arranged to sample and hold the multiple reference voltages
Implementation Method 3
the at least one second integrator may be arranged to convert at least one current clock period of the clock signal into at least one ramp signal
Implementation Method 4
the at least one comparator may be arranged to compare the at least one ramp signal with at least one reference voltage within the multiple reference voltages, to generate at least one comparison result signal
Data Source
AI summary
A clock fail detector is provided. The clock fail detector includes a timing control signal generator and a clock fail detection module, which may generate control signals according to a clock signal and perform clock fail detection according to the control signals, respectively. The clock fail detection module may comprise first integrators, sample and hold circuits, a second integrator and a comparator. The first integrator may convert previous periods of the clock signal into reference voltages according to ping pong mode control signals within the control signals, respectively. The sample and hold circuits may sample and hold the reference voltages according to the ping pong mode control signals. The second integrator may convert a current clock period of the clock signal into a ramp signal. The comparator may compare the ramp signal with a reference voltage to generate a comparison result signal for indicating whether the clock signal is normal.