Clock Synchronization Failover Using Leader Voting
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Solution Overview
Problem
Fault-tolerant computing systems require reliable clock synchronization across multiple redundant computers to maintain operation in the event of failures, but existing systems struggle to accurately identify and adapt to clock failures, especially when a single offset value is used for synchronization.
Innovation Solution
A computing system with an oscillator, counter, and processing component that maintains a synchronized clock by determining time differentials with other systems, establishing a leader clock, and re-synchronizing with an alternate clock when a failure criterion is detected, using a voting scheme to ensure robust clock synchronization and fault tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single offset value is used for clock synchronization, then the system can maintain simple synchronization logic, but the system becomes vulnerable to clock failures and cannot accurately identify or adapt to failures
Solution Approach 1:
The patent divides the single offset value into multiple offset values, each corresponding to a different computing system. Instead of maintaining one synchronization offset, the system maintains multiple offset values and selects the appropriate one based on which computing system is currently serving as the leader clock. This segmentation allows the system to isolate failures to individual offset values while maintaining overall synchronization capability through alternative offsets.
Solution Approach 2:
The system dynamically changes the offset value parameter based on the operational status of computing systems. When a failure criterion is detected, the system transitions from using a first offset value to a second offset value, effectively changing the synchronization parameter to adapt to the new operational state. This parameter change enables the system to maintain synchronization reliability despite individual system failures.
2Reliability
If the system monitors for failure criteria to detect clock failures, then the system can identify and respond to failures, but the system requires additional monitoring complexity and processing overhead
Solution Approach 1:
The system implements a feedback mechanism where computing systems continuously exchange timing information and monitor whether received data falls within expected parameters. Each system monitors the offset values and time differentials reported by other systems, and when a failure criterion is met (such as an offset value changing at a rate exceeding a threshold), the system triggers a failover process. This feedback loop enables automatic failure detection and response without requiring complex external monitoring infrastructure.
3Reliability
If the system uses a voting scheme to establish and re-synchronize with a leader clock, then the system ensures robust fault tolerance, but the system requires increased communication overhead and coordination between multiple systems
Solution Approach 1:
The patent implements a voting scheme where each computing system participates in both establishing the leader clock and monitoring for failures. Each system votes on which other system should serve as the leader based on the reported offset values and time differentials. This universal participation means that any system can become the leader and any system can detect failures, distributing the functionality across all systems rather than requiring dedicated leader election or monitoring components. The voting mechanism provides robust fault tolerance while using the existing communication infrastructure efficiently.
Data Source
AI summary
The present disclosure relates to systems and methods to maintain clock synchronization of multiple computers, or computer systems, through the exchange of communication messages that include clock and/or timing information.