Clock Failure Detection Circuit Using Delayed Edge Pulse Trains
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Solution Overview
Problem
Existing clock failure detection methods in electronic devices rely on reference clock signals or bulky analog circuits, leading to increased size, cost, and design limitations, and are not scalable or immune to noise and environmental variations.
Innovation Solution
A system and method that generates a pulse train aligned with rising and falling edges of the input clock, using a delay circuit to create a delayed clock, and a failure detection circuit to detect clock failures without requiring a reference clock signal or analog circuits, employing logic gates and flip-flops to generate a clock detection signal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If reference clock signal is used to detect clock failure, then clock failure detection capability is improved, but device size, weight, and cost increase due to additional reference clock generator and bulky counters
Solution Approach 1:
The patent extracts the essential detection function from the complex reference clock system. Instead of using a full reference clock generator and counters, the invention uses only the necessary delay elements and logic gates to detect clock failure, removing unnecessary components that contribute to weight.
Solution Approach 2:
The patent creates a simplified copy of the clock signal path using delay elements that replicate the timing behavior needed for detection. Instead of copying the entire reference clock system, only the essential timing characteristics are replicated using minimal components.
2Reliability
If reference clock signal is used to detect clock failure, then clock failure detection capability is improved, but device cost increases due to additional reference clock generator and bulky counters
Solution Approach 1:
The patent replaces expensive, complex reference clock generators and counters with inexpensive delay elements and logic gates. These simpler components are cheaper to manufacture and integrate, reducing overall device cost while maintaining detection functionality.
Solution Approach 2:
The invention extracts only the essential detection logic from the expensive reference clock system, eliminating the need for costly reference clock generators and bulky counters, thereby significantly reducing manufacturing costs.
3Reliability
If reference clock signal is used to detect clock failure, then clock failure detection capability is improved, but device complexity increases due to additional reference clock generator and bulky counters
Solution Approach 1:
The patent extracts the core detection function from the complex reference clock system, removing the reference clock generator and counters that contribute to complexity. Only the essential delay and comparison logic remains.
Solution Approach 2:
Instead of copying the entire complex reference clock system, the invention creates a minimal replication of the clock signal path using simple delay elements, significantly reducing structural complexity.
4Reliability
If analog circuits with capacitive components are used to detect clock failure, then clock failure detection capability is improved, but device size and cost increase due to bulky and expensive analog circuits
Solution Approach 1:
The patent replaces the mechanical/analog capacitive circuit system with a digital logic system using delay elements and logic gates. This substitution eliminates bulky analog components and their associated tuning requirements, reducing device area.
Solution Approach 2:
The invention replaces expensive, bulky analog capacitive circuits with inexpensive digital logic components that occupy minimal area, significantly reducing the physical footprint of the detection system.
5Reliability
If analog circuits with capacitive components are used to detect clock failure, then clock failure detection capability is improved, but device cost increases due to bulky and expensive analog circuits
Solution Approach 1:
The patent substitutes expensive analog capacitive circuits with cheaper digital logic components. This replacement eliminates the need for precision analog manufacturing and tuning, reducing production costs.
Solution Approach 2:
The invention replaces costly analog circuits with inexpensive digital logic elements that are easier and cheaper to manufacture, integrating seamlessly into standard digital fabrication processes.
6Weight of stationary object
If known solutions without reference clock signal are used to detect clock failure, then device size is reduced, but physical design limitations and timing concerns arise
Solution Approach 1:
The patent introduces adjustable delay elements that can be dynamically tuned to adapt to different physical design scenarios and timing requirements. This dynamic adjustment capability enhances physical design adaptability while maintaining the lightweight structure.
Solution Approach 2:
The invention allows adjustment of delay parameters to accommodate different timing scenarios and physical designs. By changing the delay characteristics, the system adapts to various design constraints without requiring a reference clock.
7Weight of stationary object
If known solutions without reference clock signal are used to detect clock failure, then device size is reduced, but delay balancing limitations occur
Solution Approach 1:
The patent employs adjustable delay elements that can be fine-tuned during manufacturing and operation to achieve precise delay balancing. This dynamic adjustment capability overcomes the limitations of fixed delay circuits while maintaining a lightweight design.
Solution Approach 2:
The invention enables precise control of delay parameters to achieve accurate timing balance. By adjusting the delay characteristics, the system achieves manufacturing precision comparable to reference-based solutions without the associated complexity and weight.
Data Source
AI summary
System and method for detecting clock failure are disclosed. The system includes a pulse train generator, a delay circuit, and a failure detection circuit. The pulse train generator receives an input clock and generates a pulse train including a plurality of pulses aligned with a set of rising edges and a set of falling edges of the input clock. The delay circuit delays the input clock by a first time-interval to generate a first delayed clock. The failure detection circuit receives the pulse train and the first delayed clock from the pulse train generator and the delay circuit, respectively, and generates a clock detection signal that transitions from a first logic state to a second logic state based on a failure in the input clock.