Clock Failure Error Reporting via External Clock Interface
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Solution Overview
Problem
Existing defect diagnosis circuits in circuit devices cannot accurately output error information when a failure occurs in the master clock signal, leading to incomplete or incorrect error notification to external devices.
Innovation Solution
A circuit device with a master clock signal failure detection circuit and a register unit that uses an external clock signal to store and transmit error information, independent of the master clock signal, ensuring error information is conveyed even when the master clock signal fails.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the defect diagnosis circuit operates on the basis of the master clock signal, then the defect diagnosis circuit can perform normal defect diagnosis operations, but the defect diagnosis circuit cannot output error information when a failure occurs in the master clock signal
Solution Approach 1:
The patent introduces a second clock signal as an intermediary to detect failures in the master clock signal. The second clock signal serves as a mediator that can independently monitor the master clock signal's operational status and trigger error information output when a failure is detected, thus resolving the contradiction between maintaining normal operation and ensuring error output reliability.
Solution Approach 2:
The patent segments the clock signal system into two independent parts: the master clock signal for normal operation and the second clock signal for failure detection. This segmentation allows the defect diagnosis circuit to maintain normal operations via the master clock while simultaneously enabling error information output through the second clock signal when failures occur.
2Loss of information
If the register unit takes up error information on the basis of the master clock signal, then the error information can be stored in sync with the master clock, but the register unit cannot take up and transmit error information when the master clock signal fails
Solution Approach 1:
The patent uses the second clock signal as an intermediary to enable the register unit to take up and transmit error information independently when the master clock signal fails. The second clock signal acts as a mediator that maintains the register unit's ability to capture and communicate error information even in the absence of a functioning master clock signal.
3Ease of operation
If the circuit device uses only the master clock signal for all operations, then the circuit device can maintain simple clock signal management, but the circuit device cannot detect and report master clock signal failures
Solution Approach 1:
The patent segments the clock signal management into two distinct functions: the master clock signal manages normal circuit operations while the second clock signal manages failure detection. This segmentation maintains relatively simple management for each individual clock signal while providing comprehensive failure detection capability through their independent operation.
Solution Approach 2:
The second clock signal serves multiple functions: it drives the defect diagnosis circuit during normal operation and simultaneously serves as a failure detection mechanism for the master clock signal. This multi-functionality allows the circuit to maintain simple clock signal management while gaining robust failure detection capability.
Data Source
AI summary
A circuit device includes a control circuit that operates on the basis of a master clock signal, and an interface circuit that includes a register unit and transmits data on the basis of an external clock signal which is input from an external device. In addition, the register unit takes up error information of the master clock signal on the basis of the external clock signal and stores the taken-up error information. The interface circuit transmits the data, including the error information stored in the register unit.