Clock Failure Detection Circuit for Single-Period Frequency Errors
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Solution Overview
Problem
Existing clock failure detection circuits require significant time to detect clock frequency errors, as they rely on counting multiple clock pulses and comparing counter values, which is inefficient and limited to detecting if the clock rate falls below a specified threshold.
Innovation Solution
A clock failure detection circuit with a counter that uses reset pulses based on clock edges to identify frequency errors within a single clock period, featuring two outputs for high and low frequency error detection and the ability to latch errors, enabling rapid detection and auto-reset mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If clock failure detection is performed by counting multiple clock pulses and comparing counter values, then detection accuracy is improved, but detection time increases significantly
Solution Approach 1:
The patent pre-calculates and stores the expected number of reference clock cycles corresponding to various input clock frequencies in a lookup table. When detection is needed, the system simply retrieves the pre-computed value and compares it with the actual counter value, eliminating the need to wait for multiple clock cycles to accumulate sufficient counting data. This preliminary preparation enables immediate detection with high accuracy.
Solution Approach 2:
The patent divides the detection process into two independent parts: a pre-computation phase where reference values are calculated and stored, and a real-time detection phase where only simple comparison is needed. This segmentation allows the time-consuming computation to be performed beforehand, while the actual detection operates rapidly by comparing against stored reference values.
2Productivity
If detection is performed within a single clock period, then detection speed is improved, but detection capability is limited to single-period analysis
Solution Approach 1:
The patent introduces a lookup table as an intermediary that stores pre-computed reference values. This table acts as a bridge between the single-clock-period measurement constraint and the need for accurate frequency detection. By querying the lookup table with the measured cycle count, the system can determine frequency errors with high precision without requiring extended measurement periods.
Solution Approach 2:
The system pre-computes and stores the relationship between clock cycles and frequency deviations in the lookup table during manufacturing or initialization. This preliminary action enables the detector to immediately identify frequency errors by simple comparison, achieving both high speed and high precision simultaneously.
Data Source
AI summary
A clock failure detection circuit comprises clock failure detection logic having a clock input providing an input clock signal, a counter and a reference clock input providing a reference clock signal to the counter for counting a number of reference clock cycles. The counter comprises a reset input arranged to receive successive reset pulses generated by at least one clock edge of the input clock signal to reset a counter value of the counter. The counter value before reset is used to identify a clock frequency error. A method of detecting a clock failure is also described. By using a counter value based on the reference clock cycles, and a reset trigger based on a clock edge of the input signal, it is possible to identify a clock frequency error in a much shorter time.