Clock Fault Detection Using a Mesochronous Reference Clock
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Solution Overview
Problem
Conventional functionally-safe (FuSa) systems face challenges in balancing multiple clock trees due to the need for synchronized primary and reference clocks, leading to degraded power, area, and time metrics, especially in large systems where skew management becomes impractical.
Innovation Solution
Implementing a dual-edge triggered glitch detection circuit using a mesochronous reference clock with the same frequency but different phase as the primary clock, allowing for fault detection without requiring skew-balancing of the reference clock, thereby relaxing clock tree synthesis requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock methodology with fault detection is used, then fault detection capability is achieved, but power consumption and area increase due to multiple clock trees requiring skew management
Solution Approach 1:
The patent extracts the reference clock from the synchronous skew-managed clock tree and creates an independent asynchronous reference clock path. This separation removes the requirement for skew management between primary and reference clocks, reducing the complexity and power consumption of the clock distribution network while maintaining fault detection capability through independent clock sources
Solution Approach 2:
The patent segments the clock system into independent primary clock trees and an independent asynchronous reference clock. This segmentation allows each clock tree to be optimized separately without skew constraints, reducing overall system power consumption and area while maintaining the ability to detect faults through comparison of independent clock sources
2Reliability
If conventional clock methodology with fault detection is used, then fault detection capability is achieved, but area increases due to multiple clock trees requiring skew management
Solution Approach 1:
The patent extracts the reference clock from the synchronous skew-managed clock tree and creates an independent asynchronous reference clock path. This separation removes the requirement for skew management between primary and reference clocks, reducing the complexity and power consumption of the clock distribution network while maintaining fault detection capability through independent clock sources
Solution Approach 2:
The patent segments the clock system into independent primary clock trees and an independent asynchronous reference clock. This segmentation allows each clock tree to be optimized separately without skew constraints, reducing overall system power consumption and area while maintaining the ability to detect faults through comparison of independent clock sources
3Reliability
If conventional clock methodology with fault detection is used, then fault detection capability is achieved, but time metrics degrade due to skew management requirements
Solution Approach 1:
The patent extracts the reference clock from the synchronous skew-managed clock tree and creates an independent asynchronous reference clock path. This separation removes the requirement for skew management between primary and reference clocks, reducing the complexity and power consumption of the clock distribution network while maintaining fault detection capability through independent clock sources
Data Source
AI summary
Various implementations described herein refer to an integrated circuit having first clock circuitry that receives a first clock signal and provides sampled offset pulses associated with the first clock signal when enabled with enable signals. The integrated circuit may include second clock circuitry that receives a second clock signal and provides the enable signals to the first clock circuitry based on the second clock signal. The integrated circuit may include fault detector circuitry that receives the sampled offset pulses from the first clock circuitry, receives the enable signals from the second clock circuitry, and provides one or more error flags for detected faults of the first clock signal based on the sampled offset pulses from the first clock circuitry and based on the enable signals from the second clock circuitry.