Clock Propagation Fault Detection Using Phase-Offset Timers

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Solution Overview

Problem

Existing methods for detecting faults in clock signal propagation circuits are prone to inaccuracies due to manufacturing variations, temperature, and power supply issues, and require complex production processes, including the creation of duplicate clock circuits for monitoring.

Innovation Solution

An integrated electronic circuit with a clock signal generator and propagation branches, equipped with timers and a comparator that generates an alarm signal upon detecting phase offsets in pulse signals, eliminating the need for a separate monitoring clock circuit and simplifying production by using logic circuits connected in cascade.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional monitoring methods using additional clock signals are used, then fault detection capability is improved, but manufacturing complexity and production cost increase due to requiring duplicate clock circuits

Engineering Contradiction:
Improvefault detection capabilityVSAvoidproduction complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the monitoring function with the existing clock propagation circuit by using the same physical circuit for both clock signal transmission and fault detection. The monitoring is achieved by observing the clock signal itself rather than requiring a separate monitoring circuit, thus combining multiple functions into a single circuit structure.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The clock propagation circuit serves dual purposes: it propagates the clock signal to synchronize circuit operations and simultaneously enables fault detection through monitoring the clock signal characteristics. This multi-functionality eliminates the need for dedicated monitoring hardware while maintaining detection capability.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If additional monitoring clock circuits are produced, then fault detection reliability is improved, but manufacturing precision requirements increase due to process variations affecting monitoring accuracy

Engineering Contradiction:
Improvemonitoring accuracyVSAvoidprocess variation sensitivity
Core Design Contradiction:
ReliabilityVSManufacturing precision

Solution Approach 1:

Instead of creating a separate monitoring clock circuit that would be subject to the same manufacturing variations, the patent uses the existing clock signal as the reference for monitoring. By monitoring the actual clock signal being used by the circuit, the system avoids introducing additional copies that would suffer from process variations and timing mismatches.

Inventive Principle:
Principle #26Copying

3Reliability

If environmental factors like electromagnetic interference or high-energy particles cause faults, then circuit reliability deteriorates, but adding complex protection circuits increases device complexity

Engineering Contradiction:
Improveresistance to environmental faultsVSAvoidprotection circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a feedback mechanism where the clock signal monitoring continuously checks for anomalies caused by environmental factors such as electromagnetic interference or high-energy particles. When a fault is detected through phase offset or timing deviations in the clock signal, the system can trigger protective actions to maintain circuit reliability without requiring complex preemptive protection circuits.

Inventive Principle:
Principle #23Feedback

Data Source

PatentUS11181940B2Device for detecting a fault in circuit propagating a clock signal, and corresponding method
Publication Date: 2021.11.23 STMICROELECTRONICS (GRENOBLE 2) SAS
  • US11181940B2 patent drawing
  • US11181940B2 patent drawing
  • US11181940B2 patent drawing

AI summary

An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.