Clock Generator Feedback Path for Fast Duty-Cycle Correction
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Solution Overview
Problem
Conventional clock generator circuits with feedback paths face issues of reduced responsiveness and increased power consumption due to the introduction of additional transistor circuitry, which affects clock stability and performance.
Innovation Solution
The introduction of a feedback clock path that removes circuitry from the forward path while providing power savings and duty-cycle correction capabilities, utilizing a lower frequency clock signal for phase detection and duty-cycle correction, thereby reducing the overall gate count and propagation delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional transistor circuitry is added to the forward clock path for duty-cycle correction and phase detection, then duty-cycle correction capability is improved, but propagation delay increases and responsiveness deteriorates
Solution Approach 1:
The patent segments the clock path into forward and feedback paths. The forward path contains only essential circuits (coarse delay line, fine delay line, output buffer) for fast clock generation, while the feedback path contains duty-cycle correction circuits and phase detection circuits. This segmentation allows duty-cycle correction without adding delay to the forward clock path, resolving the contradiction between correction capability and responsiveness.
Solution Approach 2:
The patent introduces a feedback clock path as an intermediary mechanism. Instead of adding correction circuits directly to the forward path, the system uses the feedback path to carry corrected clock signals and phase detection signals. This intermediary approach enables duty-cycle correction while keeping the forward path clean and fast.
2Adaptability or versatility
If additional transistor circuitry is added to the forward clock path for duty-cycle correction and phase detection, then duty-cycle correction capability is improved, but power consumption increases
Solution Approach 1:
The patent segments the clock path into forward and feedback paths, placing power-consuming duty-cycle correction circuits and phase detection circuits in the feedback path rather than the forward path. This segmentation reduces power consumption in the critical forward clock path while maintaining correction capabilities in the feedback path.
Solution Approach 2:
The feedback clock path serves as an intermediary that carries corrected clock signals and phase detection signals separately from the main forward clock path. This allows power-consuming correction and detection circuits to operate without increasing power consumption of the forward path, resolving the contradiction between correction capability and power efficiency.
3Adaptability or versatility
If additional transistor circuitry is added to the forward clock path, then duty-cycle correction is enabled, but device complexity increases
Solution Approach 1:
The patent segments the clock generator into forward path components (coarse delay line, fine delay line, output buffer) and feedback path components (duty-cycle correction circuits, phase detection circuits). This segmentation organizes complexity into functional modules, making the overall device more manageable and maintainable while enabling duty-cycle correction.
Solution Approach 2:
The feedback clock path acts as an intermediary structure that houses duty-cycle correction and phase detection circuits separately from the forward path. This organizational approach reduces overall device complexity by clearly separating correction functionality from clock generation functionality, making the system easier to design and maintain.
Data Source
AI summary
Memories, clock generators and methods for providing an output clock signal are disclosed. One such method includes delaying a buffered clock signal by a adjustable delay to provide an output clock signal, providing a feedback clock signal from the output clock signal, and adjusting a duty cycle of the buffered clock signal based at least in part on the feedback clock signal. An example clock generator includes a forward clock path configured to provide a delayed output clock signal from a clock driver circuit, and further includes a feedback clock path configured to provide a feedback clock signal based at least in part on the delayed output clock signal, for example, frequency dividing the delayed output clock signal. The feedback clock path further configured to control adjustment a duty cycle of the buffered input clock signal based at least in part on the feedback clock signal.