Clock Transmission Circuit With Feedback Impedance for Low Delay
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Solution Overview
Problem
As semiconductor devices operate at higher frequencies, accurately supplying clock signals becomes challenging due to increased propagation delay and reduced pulse width, making it difficult to maintain timing accuracy.
Innovation Solution
A clock transmission circuit is designed with a feedback impedance circuit connected in parallel to an inverter and an inverter chain unit with an odd number of smaller inverters, minimizing propagation delay through complementary reduction of swing level and de-emphasis operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of the clock signal increases, then the operating speed of the semiconductor device is improved, but the propagation delay increases and timing accuracy deteriorates
Solution Approach 1:
The clock transmission path is segmented into multiple stages: a first inverter for initial signal generation, a feedback impedance circuit for signal conditioning, and an inverter chain unit with multiple smaller inverters for distributed transmission. This segmentation allows each stage to be optimized independently, reducing overall propagation delay while maintaining timing accuracy at high frequencies.
Solution Approach 2:
Different portions of the clock transmission circuit are given different characteristics: the first inverter uses larger size for strong driving capability, the feedback impedance circuit provides localized signal conditioning, and the inverter chain uses smaller inverters distributed along the transmission path. This local optimization of circuit characteristics minimizes propagation delay across the entire transmission path.
2Speed
If the frequency of the clock signal increases, then the operating speed is improved, but the pulse width decreases making accurate supply difficult
Solution Approach 1:
A feedback impedance circuit is introduced that connects the output of the first inverter back to its input through an impedance element. This feedback mechanism compensates for signal degradation and maintains pulse width integrity even at high frequencies where pulse width naturally decreases, ensuring accurate clock signal supply throughout the transmission path.
3Measurement precision
If a de-emphasis operation is performed to accurately drive the clock signal, then timing accuracy is improved, but circuit complexity increases
Solution Approach 1:
The inverter chain unit employs inverters with progressively smaller sizes along the transmission path, changing the driving strength parameter to compensate for signal degradation. This parameter variation approach achieves de-emphasis operation and maintains timing accuracy without requiring complex control circuits or additional components, thus limiting the increase in circuit complexity.
4Loss of time
If the size of inverters is reduced to minimize propagation delay, then propagation delay is reduced, but driving capability deteriorates
Solution Approach 1:
The clock transmission circuit uses asymmetric inverter sizing: the first inverter is larger to provide strong initial driving capability, while the subsequent inverters in the chain are smaller to minimize propagation delay. This asymmetric configuration balances driving capability and speed requirements, with the feedback impedance circuit compensating for the reduced driving strength of smaller inverters.
Data Source
AI summary
A clock transmission circuit comprising a first inverter configured to invert an input clock signal received through a clock input terminal to generate an inverted clock signal, and output the inverted clock signal to a clock output terminal, a feedback impedance circuit connected in parallel with the first inverter between the clock output terminal and the clock input terminal, and an inverter chain unit having a smaller size than the first inverter, including an odd number of second inverters connected in a chain form, connected to the clock output terminal, and configured to invert the inverted clock signal to generate an output clock signal and output the output clock signal to the clock output terminal.