Clock Generator Feedback Circuit for Stable Pulse Width
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Solution Overview
Problem
Existing digital clock generators using ring oscillators with delay-lock-loop (DLL) cells face issues with oscillation discontinuation due to varying delay times between rise and fall signals, leading to distorted pulses and potential clock signal switch-off.
Innovation Solution
A clock recovery circuit is designed with a feedback signal generated via a flip-flop set and reset by pulses from DLL cells at the end and middle of the delay line, ensuring continuous clock signal generation as long as an enable pin is set, while compensating for Process, Voltage, Temperature (PVT) variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If DLL cells are used to generate clock signals with simple and low-power design, then power consumption and cost are reduced, but oscillation stability deteriorates due to varying delay times causing pulse distortion
Solution Approach 1:
The patent implements a feedback mechanism where the output of the last delay cell is fed back to the input of the first delay cell, creating a closed-loop system. This feedback ensures that the clock signal continues to oscillate by continuously regenerating the input signal, thereby maintaining oscillation stability without requiring additional power-consuming components.
Solution Approach 2:
The patent introduces a preliminary inversion stage that inverts the signal before it enters the delay line. This preliminary action compensates for the pulse distortion that occurs during propagation through the delay cells, ensuring that the pulse width remains sufficient to maintain reliable oscillation throughout the circuit's operation.
2Device complexity
If delay cells introduce different delays for rise and fall signals, then the circuit operates with simple delay elements, but pulse width decreases to zero causing clock switch-off
Solution Approach 1:
The patent deliberately introduces asymmetry by placing an inverter at a specific position within the delay line (not at the beginning or end). This asymmetric configuration compensates for the inherent asymmetry in rise and fall delays, balancing the pulse widths and preventing them from decreasing to zero.
Solution Approach 2:
The patent addresses the pulse width issue by adding a spatial dimension to the solution - inserting an inverter stage at a specific position along the delay line. This dimensional approach (adding a stage at a specific location) allows compensation for delay asymmetry without increasing overall circuit complexity significantly.
3Measurement precision
If multiple delay cells are used to achieve precise clock generation, then clock accuracy improves, but sensitivity to PVT variations increases
Solution Approach 1:
The patent implements a self-calibrating mechanism where the feedback loop automatically adjusts to PVT variations. The closed-loop configuration allows the system to self-correct for delays introduced by process, voltage, and temperature changes, maintaining clock accuracy without requiring external calibration circuits or additional control components.
Data Source
AI summary
In an embodiment, a circuit includes cascaded delay units arranged in a chain, each delay unit having an input-to-output delay time, wherein a first delay unit in the chain is configured to receive an input signal for propagating along the delay units in the chain, logic circuitry coupled to delay units in the chain, the logic circuitry configured to generate a clock signal as a logic combination of signals input to and output from the delay units in the chain and feedback circuitry configured to supply to the first delay unit in the chain a feedback signal, the feedback circuitry including a first feedback signal path from a last delay unit in the chain to the first delay unit in the chain and a second feedback signal path from an intermediate delay unit in the chain to the first delay unit in the chain, the intermediate delay unit arranged between the first delay unit in the chain and the last delay unit in the chain.