Clock Circuit Feedback Loop for PVT-Stable Frequency Control
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Solution Overview
Problem
Existing clock circuits in microcontroller units (MCUs) and microprocessor units (MPUs) are affected by variations in process, voltage, and temperature, leading to inconsistent output frequencies.
Innovation Solution
A clock circuit design incorporating a reference and feedback branch with variable capacitors and resistors, along with dividers and inverters, forms an analog frequency lock loop to stabilize the output frequency, compensating for these variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a programmable clock circuit is used to generate various frequencies, then frequency flexibility is improved, but frequency stability deteriorates due to process, voltage, and temperature variations
Solution Approach 1:
The patent implements a feedback mechanism where the output clock signal is fed back through a feedback branch containing switches and RC networks. The feedback signal is compared with the reference signal in an amplifier, and the difference is used to adjust the VCO input, thereby stabilizing the output frequency against PVT variations while maintaining programmable frequency flexibility through control signals.
Solution Approach 2:
The patent uses programmable switches to change the resistance and capacitance values in the reference and feedback branches based on control signals. By dynamically adjusting these parameters, the circuit maintains accurate frequency multiplication ratios across different operating conditions, resolving the contradiction between frequency flexibility and stability.
2Adaptability or versatility
If frequency multiplication is implemented using programmable switches and RC networks, then frequency flexibility is improved, but sensitivity to PVT variations increases
Solution Approach 1:
The feedback branch mirrors the reference branch structure with corresponding switches and RC networks. The feedback signal undergoes the same PVT variations as the reference signal, and when compared in the amplifier, the common-mode variations are rejected. This differential approach cancels out the harmful PVT effects while preserving the frequency multiplication capability.
Solution Approach 2:
The patent creates equipotential conditions by using matched RC networks in both reference and feedback paths. The switches in corresponding positions are controlled to maintain equal voltage divisions, ensuring that PVT variations affect both paths equally and can be differentialled out, thus reducing sensitivity while maintaining frequency multiplication.
3Reliability
If an analog frequency lock loop is constructed with variable resistors and capacitors, then frequency stability is improved, but circuit complexity increases
Solution Approach 1:
The frequency lock loop is segmented into modular reference and feedback branches, each containing identical sub-components (switches, RC networks). This segmentation allows independent optimization of each branch while simplifying the overall design through repetition of proven sub-circuits, reducing the perceived complexity despite the enhanced stability functionality.
Solution Approach 2:
The same circuit topology and component types are used in both reference and feedback branches, making the design universal and easier to implement. The programmable switches serve multiple functions: frequency multiplication, PVT compensation, and loop control, thereby achieving frequency stability without proportionally increasing circuit complexity.
Data Source
AI summary
A clock circuit comprising a voltage-controlled oscillator having an input coupled to an output of an amplifier, and an output, outputting an output clock signal. The clock circuit further comprises, a reference branch and a feedback branch, both comprising, a first switch coupled to an input via an inverter and a second switch coupled to the input. The branches also both comprise, a variable capacitor coupled to a reference potential and coupled to the first switch, and a variable resistor coupled to the first switch. Both branches comprise a supply voltage coupled to the variable resistor and an output node, wherein the second switch is coupled to the variable capacitor and coupled to a node. The reference branch input is an input clock signal and the output is a reference voltage, and the feedback branch input is an output clock signal and the output is a feedback voltage.