Programmable Clock Input Filtering With Duty Cycle Adjustment
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Solution Overview
Problem
Existing clock input filter circuits are large, consume significant static power, and lack programmability to adjust the duty cycle of output signals, making them inefficient and inflexible.
Innovation Solution
A clock input filter using programmable low-pass delay elements to filter input signals during both low and high periods, with output multiplexing to adjust duty cycle, consuming minimal static power and no analog differential comparators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock input filter circuits use analog comparators and delay circuits, then filtering function is achieved, but circuit area and static power consumption increase
Solution Approach 1:
The patent replaces analog comparator-based mechanical/electronic filtering systems with a digital logic-based system using programmable delay elements, logic gates, and multiplexers. This substitution reduces circuit area while maintaining filtering functionality through digital signal processing techniques.
Solution Approach 2:
The patent introduces programmable delay elements with adjustable delay parameters that can be configured via control signals. This allows the filtering characteristics to be dynamically adjusted without changing the physical circuit structure, reducing the need for multiple fixed-filter circuits and thereby reducing overall circuit area.
2Reliability
If traditional clock input filter circuits use analog comparators and intercoupled delay circuits, then filtering is provided, but static power consumption increases
Solution Approach 1:
The patent replaces power-hungry analog comparator circuits with digital logic circuits consisting of programmable delay elements, logic gates (AND, OR, NOT), and multiplexers. Digital logic circuits generally consume less static power than analog comparators, especially when implemented in modern CMOS technology.
Solution Approach 2:
The patent uses clocked operation where filtering is performed synchronously with the input clock signal. The programmable delay elements and logic gates operate periodically based on clock edges, allowing the circuit to enter low-power states between active periods, thereby reducing average static power consumption.
3Device complexity
If fixed delay circuits are used in clock input filters, then simple circuit structure is maintained, but duty cycle adjustment capability is lost
Solution Approach 1:
The patent introduces programmable delay elements whose delay characteristics can be dynamically adjusted via control signals. This dynamic adjustability allows the circuit to modify its filtering behavior and duty cycle output without requiring multiple fixed circuits, achieving versatility while maintaining relatively simple circuit structure.
Solution Approach 2:
The patent designs a universal filtering circuit that can perform multiple functions: standard filtering, duty cycle adjustment, and glitch rejection. The programmable delay elements and multiplexer configuration allow a single circuit structure to adapt to different operating requirements, eliminating the need for separate circuits for each function.
4Device complexity
If no duty cycle adjustment capability is provided, then circuit simplicity is maintained, but versatility and processor configurability are reduced
Solution Approach 1:
The patent implements dynamic duty cycle adjustment through programmable delay elements that respond to control signals from a processor or external source. This allows the circuit to be reconfigured in real-time to meet different application requirements while maintaining a relatively simple base circuit structure.
Solution Approach 2:
The patent enables processor configurability by allowing delay parameters and multiplexer selection to be controlled via digital control signals. This parameter adjustability provides versatility for different duty cycle requirements without fundamentally changing the circuit architecture, balancing simplicity with adaptability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides a compact, low-power clock input filter that adjusts duty cycle efficiently, maintaining glitch-free output with minimal static power consumption and flexibility to vary duty cycle within standard process, temperature, and voltage ranges.
Implementation Method 1
The first programmable low-pass delay element includes a first RC network, the RC time constant of which is controllable by a processor. Similarly, the second programmable low-pass delay element includes a second RC network, the RC time constant of which is controllable by the processor.
Data Source
AI summary
A clock input filter uses a first programmable low-pass delay element to filter during a low period of an input clock signal and to output a SET signal. The clock input filter uses a second programmable low-pass delay element to filter during a high period of the input clock signal and to output a RESET signal. A latch is set and reset by the SET and RESET signals. The latch outputs a filtered version of the input signal that has the same approximate duty cycle as the input signal. A pair of gates generates a corresponding pair of duty cycle adjusted versions of the input signal. Output multiplexing circuitry is provided to output either the output of the latch, or an increased duty cycle version of the input signal, or a decreased duty cycle version of the input signal, or an unfiltered version of the input signal.