Clock Filter Switching with Feedback Logic for Glitch-Free Handover
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Solution Overview
Problem
Existing clock filter systems face challenges in efficiently switching between different cutoff frequencies without generating glitches and turning off unused clock filters, leading to high power consumption and potential circuit failures due to asynchronous issues.
Innovation Solution
A clock filter system with a feedback logic circuit and clock control circuits that control individual clock signals to be turned on or off at different times, using a bypass mode to manage voltage transitions and prevent glitches, and turning off unused filters to conserve power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple clock filters are kept on to support multiple voltages, then voltage adaptability is improved, but power consumption increases
Solution Approach 1:
The feedback logic circuit performs preliminary detection of enable signals before switching occurs. By detecting whether clock filters are enabled in advance, the system can prepare appropriate control signals to ensure smooth switching without requiring all filters to remain continuously powered on, thus reducing power consumption while maintaining voltage adaptability.
Solution Approach 2:
The feedback logic circuit continuously monitors the enable signals from multiple clock filters and adjusts control signals accordingly. This feedback mechanism allows the system to dynamically power down unused clock filters while maintaining support for multiple voltages, resolving the contradiction between adaptability and power consumption.
2Ease of operation
If a multiplexer is used to switch clock filters, then switching capability is improved, but glitch generation occurs
Solution Approach 1:
The feedback logic circuit acts as an intermediary between the multiplexer and clock filters. It detects the enable signals and generates intermediate control signals that coordinate the switching process, ensuring that the multiplexer switches clock filters without generating glitches, thus maintaining switching capability while eliminating harmful glitch generation.
3Object-generated harmful factors
If clock source is turned off before switching, then glitch generation is avoided, but clock availability is lost
Solution Approach 1:
The feedback logic circuit performs preliminary detection of the clock source status before switching. By detecting whether the clock source is active in advance, the system can generate appropriate control signals to maintain clock availability during switching, avoiding the need to turn off the clock source entirely while still preventing glitch generation.
4Reliability
If all clock filters are turned on for switching, then switching reliability is improved, but power consumption increases
Solution Approach 1:
The feedback logic circuit monitors enable signals from clock filters and dynamically adjusts which filters remain powered on. This feedback mechanism ensures that only the necessary clock filters are kept active for switching operations, maintaining switching reliability while minimizing power consumption by powering down unused filters.
Solution Approach 2:
The system temporarily discards (powers down) clock filters that are not currently needed for switching operations. The feedback logic circuit ensures that filters can be quickly recovered (powered back on) when needed, maintaining switching reliability while reducing power consumption during normal operation.
Data Source
AI summary
A clock filter system and a clock filter switching method. The clock filter system includes a plurality of clock filters for respectively outputting a plurality of individual clock signals; a bypass circuit for outputting a bypass enable signal; a plurality of clock enable circuits for respectively outputting a plurality of enable signals; a feedback logic circuit for performing an inverse OR (NOR) operation on the bypass enable signal and the plurality of enable signals to generate a feedback signal; a plurality of clock control circuits for respectively generating and outputting a plurality of control signals according to the feedback signal and the plurality of enable signals to respectively control the plurality of individual clock signals to be turned on or turned off. When switching clock filters, a source individual clock signal and a target individual clock signal are controlled to be turned on at different times.