Clock Filter Circuit for Glitch-Free Signal Timing
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Solution Overview
Problem
Noise interference in clock signals generated by clock generators in electronic devices can lead to glitches, causing errors in circuit outputs.
Innovation Solution
A clock filter system comprising delay circuits and setting circuits that invert, delay, and synchronize clock signals to generate a glitch-free output clock, using first and second delay times that are equal to or less than half a clock cycle, and employing SR flip-flops and NOR gates to manage signal levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a clock generator is used to provide clock signals to control circuits, then the functionality and performance of electronic devices are improved, but noise interference may cause glitches in the clock signals which lead to errors in circuit outputs
Solution Approach 1:
The patent introduces a clock filter as an intermediary component between the clock generator and the control circuits. This filter includes delay circuits and setting circuits that process the clock signal to remove glitches while preserving the essential timing information, thus mediating between the noisy source and the sensitive load
Solution Approach 2:
The clock filter performs preliminary processing of the clock signal by generating delayed versions of the clock and using these to detect and eliminate glitches before the signal reaches the control circuits. This preliminary action prevents errors before they can occur in the main system
2Reliability
If delay circuits are used to filter glitches in clock signals, then signal stability is improved, but the circuit complexity increases due to multiple delay circuits and setting circuits
Solution Approach 1:
The clock filter is segmented into distinct functional modules: delay circuits for generating time-shifted versions of the clock signal, and setting circuits for combining these delayed signals to eliminate glitches. This segmentation makes the complex filtering function manageable and implementable using standard circuit components
Solution Approach 2:
The invention changes the time parameter of the clock signal by introducing controlled delays that are equal to or less than half a clock cycle. By adjusting these delay parameters, the circuit can effectively filter glitches while maintaining the original clock frequency and timing characteristics
Data Source
AI summary
A clock filter filtering a glitch of an input clock to generate an output clock is provided. A first delay circuit inverts the input clock to generate an inverted clock and delays the inverted clock to generate a first processing clock. A second delay circuit delays the input clock to generate a second processing clock. A first setting circuit generates a reset clock according to the inverted clock and the first processing clock. A second setting circuit generates a set clock according to the input clock and the second processing clock. When the set clock changes from a first level to a second level, a third setting circuit sets the output clock at the second level. When the reset clock changes from the first level to the second level, the third setting circuit sets the output clock to the first level.