Clock Signal Flipping for Accurate Duty Cycle Measurement
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Solution Overview
Problem
Existing duty cycle measurement techniques for clock signals are limited by random and deterministic noise, leading to inaccurate calibration and correction of clock signal duty cycles, which can affect the performance of circuits relying on both rising and falling edges.
Innovation Solution
A clock test system that generates multiple clock signals of a common frequency, allowing for selective switching between these signals during different time periods to cancel static offsets in duty-cycle distortion measurements, thereby improving measurement accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a single clock signal is used for duty cycle measurement, then the measurement process is simple, but the measurement accuracy is reduced due to random and deterministic noise
Solution Approach 1:
The patent segments the clock signal measurement process by generating multiple clock signals (e.g., inverted pairs) and measuring their duty cycles separately. By dividing the measurement into multiple segments and combining the results, the patent cancels out static offsets and reduces noise, thereby improving measurement precision while managing complexity through systematic segmentation
Solution Approach 2:
The patent creates copies of the clock signal in inverted form (e.g., clk and clk_bar) and measures the duty cycle of each copy. By copying the signal and measuring multiple versions, the system can compare and combine measurements to eliminate common-mode errors and improve accuracy without requiring fundamentally new measurement techniques
2Measurement precision
If multiple clock signals are generated and switched between them, then measurement accuracy improves through offset cancellation, but the device complexity increases
Solution Approach 1:
The patent implements periodic switching between multiple clock signals in a systematic sequence (e.g., alternating between clk and clk_bar over multiple periods). This periodic action allows the measurement system to sample different signal versions at regular intervals, enabling statistical processing and offset cancellation that improves precision while maintaining manageable complexity through rhythmic, predictable operation
Solution Approach 2:
The patent merges multiple duty cycle measurements from different clock signal copies by calculating their average or difference. By combining the measurement results from multiple signals in a systematic way, the patent cancels out static offsets and reduces random noise, achieving higher precision while the merging process itself provides a structured approach to managing system complexity
Data Source
AI summary
A clock test system included in a computer system includes a clock generator circuit that generates multiple clock signals. A switch circuit selects different ones of the multiple clock signals during different time periods to generate an output clock signal. A measurement circuit measures a duty cycle of the output clock signals during the different time periods to generate multiple duty cycle measures. The measurement circuit uses the multiple duty cycle measurements to cancel a portion of duty cycle distortion in the output clock signal to determine an adjusted duty cycle value.