Clock-Forwarded Display Signaling With Back-Channel Delay Correction
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Solution Overview
Problem
Existing systems for transmitting data in digital displays face challenges in maintaining the correlation between clock jitter and data jitter, leading to irregular timing margins and limited data rates due to inherent filtering in clock and data recovery circuits, and asymmetrical noise levels between transmitters and receivers.
Innovation Solution
A system that transmits a sampling clock with data, using delay adjust circuits in the transmitter to measure and adjust delay errors via a back channel, ensuring correlation between clock and data jitter, and employing phase locked loops and variable delay lines to optimize timing margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a low-frequency clock is transmitted and phase-locked loops are used to multiply the clock frequency, then the required sampling clock rate is achieved, but the correlation between clock jitter and data jitter is lost due to low-pass filtering in the PLL
Solution Approach 1:
The patent extracts the sampling clock from the transmitted data stream itself rather than using a separate low-frequency clock that requires PLL multiplication. By embedding the sample-rate clock directly in the data transitions, the system achieves the required sampling rate without introducing PLL filtering that would decorrelate clock and data jitter.
Solution Approach 2:
The patent merges the data transmission and clock transmission into a single channel. The sampling clock is derived from transitions in the data sequence itself, combining what were previously separate signals (data and clock) into one unified transmission medium, thereby preserving jitter correlation.
2Ease of operation
If clock and data are transmitted separately, then the receiver can use independent clock recovery, but the timing correlation between clock and data jitter is reduced
Solution Approach 1:
The patent combines clock and data transmission into a single integrated signal. The data is transmitted with embedded transitions that simultaneously carry both information and timing reference, eliminating the need for separate clock recovery while preserving jitter correlation.
3Measurement precision
If transition encoding is applied to ensure frequent transitions, then clock recovery is improved, but the system complexity increases due to required CDR circuits
Solution Approach 1:
The patent extracts the sampling clock directly from data transitions without requiring complex CDR circuits. By using the inherent transitions in the data sequence as the clock source, the system simplifies the receiver architecture while maintaining accurate timing recovery.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach preserves the correlation between clock and data jitter, enhancing timing margins and allowing for higher data rates with reduced errors, while maintaining precision circuitry in the transmitter.
Implementation Method 1
the driver ICs receive a low-frequency clock from the transmitter, and use a phase-locked loop (PLL) to multiply the clock frequency to the required rate for sampling the received data
Data Source
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AI summary
A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.