Clock-Forwarded Serial Link for Zero-Cycle Die-to-Die Transfer
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Solution Overview
Problem
High-performance computing applications require substantial processing power and high-bandwidth data communication between dice, which consumes significant power, especially in die-to-die communication within an IC package.
Innovation Solution
Implement clock-forwarded serial links with a clock lane and data lanes, using the same clock edges to transmit and latch data, and employ source-side clock calibration to synchronize data transfer without additional cycles, along with deserializer clock forwarding and FIFO buffering to achieve zero-cycle or short-cycle data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high bandwidth data communication is implemented between dice, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent implements clock gating where the serial clock is periodically enabled only during valid data transfer cycles and disabled during idle cycles. This periodic activation of the clock signal reduces power consumption by minimizing clock edges during idle periods while maintaining high-speed data transfer capability when needed.
Solution Approach 2:
The patent changes the operational parameters of the data link by introducing valid signal control that enables or disables data transmission based on whether data is actually being transferred. This parameter change allows the system to switch between high-speed operation mode and low-power idle mode, resolving the contradiction between speed and power consumption.
2Loss of time
If zero-cycle data transfer is implemented, then data transfer latency is reduced, but timing control complexity increases
Solution Approach 1:
The patent merges the clock signal and valid signal into a unified timing control mechanism where the same clock edges that drive data transmission also serve as the timing reference for data latching. This merging eliminates the need for separate timing control signals and reduces overall timing control complexity while achieving zero-cycle transfer.
Solution Approach 2:
The serial clock signal serves dual purposes: it both drives the data transmission and provides the timing reference for receiving the data. This self-service approach where the clock signal performs multiple functions simplifies the timing control architecture while enabling zero-cycle data transfer.
3Device complexity
If clock edges are used to both drive and latch data, then device complexity is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies preliminary action by introducing source-side clock calibration that pre-adjusts the timing of clock edges before they are transmitted. This calibration compensates for potential timing skew and ensures that the clock edges arrive at the correct time relative to data valid edges, thereby meeting manufacturing precision requirements without increasing device complexity.
Data Source
AI summary
Systems and methods are disclosed for reduced-power serial data links. A clock-forwarded serial link carries a clock lane and one or more data lanes. Every active serial data cycle is accompanied by its own serial clock edge: a clock delay allows the same clock edge to drive data at a transmitter and latch data at a receiver. Power is saved by idling the serial clock when data is not being transmitted. A valid signal can be omitted, providing a space saving. At the destination, similar clock-forwarding and delay enables a single parallel clock edge to drive data to the boundary of its clock domain, e.g. from a deserializer to a FIFO. The data link exhibits zero-cycle entry and exit. Variations with half- or single-cycle entry or exit are disclosed.