Clock Forwarding Repeater Circuit for Jitter-Filtered High-Speed Links
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Solution Overview
Problem
Repeater circuits in high-speed links suffer from cycle-to-cycle jitter contamination due to noise introduced by clock amplifiers, limiting the length of copper cable links and increasing system complexity and cost when optical cables are used.
Innovation Solution
A repeater circuit with a clock multiplier unit and phase interpolator that generates an internal clock signal and filters cycle-to-cycle jitter by providing an output clock signal as a weighted average of the forwarded and internal clock signals, allowing longer copper cable links and reducing system costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional clock forwarding is used with clock amplifiers in repeater circuits, then the link can operate at high data rates, but cycle-to-cycle jitter accumulates and contaminates the forwarded clock signal, limiting the maximum link length to less than 10 meters
Solution Approach 1:
The patent extracts and removes the harmful cycle-to-cycle jitter from the forwarded clock signal by using a separate internal clock source that is isolated from the accumulated jitter of multiple repeater stages. The CMU generates a clean internal clock signal that does not contain the jitter contamination present in the forwarded clock signal after passing through multiple amplifiers.
Solution Approach 2:
The patent introduces an intermediary phase interpolator that combines the forwarded clock signal with the clean internal clock signal from the CMU. This intermediary device performs phase interpolation to generate an output clock signal that has reduced jitter compared to the forwarded clock signal alone, effectively mediating between the two clock sources to produce a superior clock signal.
2Length of stationary object
If the number of repeater circuits is increased to extend the link length, then the link can cover longer distances, but the cycle-to-cycle jitter contamination increases, limiting the effective link length
Solution Approach 1:
The patent extracts the harmful jitter component from the clock signal path by using an independent internal clock source generated by the CMU. This internal clock signal does not accumulate jitter from multiple repeater stages, allowing the link to be extended by adding more repeaters without proportionally increasing jitter contamination.
Solution Approach 2:
The patent implements a feedback mechanism where the phase interpolator continuously adjusts the output clock signal by interpolating between the forwarded clock signal and the internal clock signal from the CMU. This feedback approach allows the system to maintain low jitter even as the number of repeater circuits increases, enabling extended link lengths.
3Length of stationary object
If optical cables are used to extend the link length beyond copper cable limitations, then the link can achieve longer distances, but the system cost and complexity increase
Solution Approach 1:
The patent uses inexpensive copper cable instead of expensive optical cable by implementing the jitter reduction technique that enables long-distance copper cable operation. The CMU and phase interpolator allow copper cable to effectively replace optical cable for link extensions, avoiding the high cost and complexity of optical infrastructure while achieving the same link length extension goal.
4Length of stationary object
If more repeater circuits are added to extend the link, then the link length increases, but the device complexity and cost increase
Solution Approach 1:
The patent implements a universal clock management architecture where the CMU and phase interpolator can be integrated into any repeater circuit in the link. This multi-functional design allows the same jitter reduction mechanism to be applied at any point in the link, providing a scalable solution that maintains low complexity while enabling link extension through additional repeaters.
Data Source
AI summary
A repeater circuit, such as a clock regeneration and multiplication circuit, is described. In this repeater circuit, a clock multiplier unit (CMU) generates an internal clock signal based on a forwarded clock signal, which is received on a link. Furthermore, a phase interpolator (PI) in the repeater circuit provides the output clock signal based on the forwarded clock signal and the internal clock signal. Note that the CMU and the PI filter reduce the cycle-to-cycle jitter in the forwarded clock signal and the internal clock signal, and that the output clock signal has a phase that is a weighted average of the phases of the forwarded clock signal and the internal clock signal. In addition, the relative weights of the forwarded clock signal and the internal clock signal (i.e., the amount of phase averaging and jitter filtering) may be adjusted based on a position or location on the link.