Clock Forwarding Multiplexer for Continuous Signal Delivery
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Solution Overview
Problem
Existing high-speed communication systems require an external clock generator, increasing system cost and power consumption, and face disruptions during data rate changes due to PLL relocking, which affects the continuous transmission of reference clock signals.
Innovation Solution
A clock forwarding scheme that uses a multiplexer to switch between a primary and secondary reference clock signal during data rate changes, allowing the secondary clock signal to be generated with less stringent timing requirements, reducing power and area consumption, and ensuring continuous reference clock delivery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an external clock generator is used, then the reference clock signal can be provided, but system cost and power consumption increase
Solution Approach 1:
The patent extracts the clock generation function from an external component and relocates it to an internal PLL (Phase-Locked Loop) within the communication device. This eliminates the need for an external clock generator, thereby reducing system cost and power consumption while maintaining the reference clock signal provision
Solution Approach 2:
The PLL is designed to serve multiple functions: generating the reference clock signal for normal data transmission and enabling seamless data rate changes. By making the PLL multi-functional, the system eliminates dedicated external clock components, reducing overall system complexity and power consumption
2Reliability
If an external clock generator is used, then the reference clock signal can be provided, but system cost increases
Solution Approach 1:
The patent removes the external clock generator from the system architecture and integrates the clock generation function into the internal PLL, thereby reducing the number of external components and simplifying the overall system while maintaining reference clock signal provision
Solution Approach 2:
The patent combines the clock generation function with the existing PLL data processing path, merging previously separate functions (external clock generation and internal data processing) into a unified internal system, thereby reducing component count and system cost
3Adaptability or versatility
If PLL relocking is performed during data rate changes, then data rate adaptation is achieved, but reference clock signal transmission is disrupted
Solution Approach 1:
The patent performs preliminary action by capturing and storing the reference clock signal in a buffer or memory element before the PLL relocking process begins. This pre-capture ensures that the reference clock signal transmission continues uninterrupted during the data rate transition, as the stored signal can be forwarded while the PLL reconfigures
Solution Approach 2:
The patent introduces an intermediary mechanism (such as a buffer or delay element) that temporarily holds the reference clock signal during PLL relocking. This intermediary allows the signal to be preserved and continuously transmitted even while the PLL undergoes reconfiguration for data rate changes
Data Source
AI summary
In certain aspects, an apparatus includes a multiplexer having a first input, a second input, a select input, and an output, wherein the first input is configured to receive a first reference clock signal, the second input is configured to receive a second reference clock signal, and the select input is configured to receive a select signal. The multiplexer is configured to select one of the first and second reference clock signals based on the select signal, and output the selected one of the first and second reference clock signals at the output of the multiplexer. The apparatus also includes a clock driver having an input and an output, wherein the input of the clock driver is coupled to the output of the multiplexer.