Clock Distribution Circuit for Fractional Division With Lower Delay
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Solution Overview
Problem
Existing clock distribution devices struggle to efficiently distribute input clock signals, particularly those requiring fractional division ratios, due to delays caused by flip-flops and logic gates.
Innovation Solution
A clock distribution device comprising a latch and a flip-flop, along with NAND and OR gates, is used to generate an output clock signal with a fractional division ratio based on a single-frequency input clock signal, simplifying the distribution process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If three flip-flops, an AND gate, and an OR gate are used to generate fractional division ratio clock signals, then the clock distribution device can output clock signals in various multiples, but significant delay occurs in the final output clock signal due to the delay elements
Solution Approach 1:
The patent extracts and removes the delay-causing elements (AND gate and OR gate) from the clock distribution circuit. By eliminating these logic gates that introduce significant delay, the patent achieves fractional division ratio clock signal generation with minimal delay, resolving the contradiction between versatility and time loss.
Solution Approach 2:
The patent segments the clock distribution function into separate components: a latch for generating first clock signals and a flip-flop for generating second clock signals. This segmentation allows each component to perform its function independently without the need for additional delay-introducing logic gates, thereby reducing overall signal delay while maintaining the capability to output clock signals in various multiples.
2Adaptability or versatility
If a clock doubler is used to output clock signals in various multiples, then the device can generate fractional division ratios, but high-frequency clock signals are required which may not be easily implemented
Solution Approach 1:
The patent replaces the complex clock doubler circuit with simpler, more easily implementable components (latch and flip-flop). These simpler components can be easily manufactured and integrated without requiring high-frequency clock signals, making the implementation much easier while still achieving fractional division ratio generation.
Solution Approach 2:
The patent changes the operating parameters by using standard frequency clock signals instead of high-frequency clock signals. By modifying the frequency requirements and using appropriate latch and flip-flop configurations, the patent achieves fractional division ratios without the implementation difficulties associated with high-frequency operation.
3Adaptability or versatility
If multiple logic gates are used in the clock distribution device, then various clock signal multiples can be generated, but power consumption increases
Solution Approach 1:
The patent removes unnecessary logic gates (AND gate and OR gate) from the clock distribution circuit. By extracting these power-consuming components and replacing them with simpler latch and flip-flop based architecture, the patent significantly reduces power consumption while maintaining the capability to distribute clock signals in various multiples.
Data Source
AI summary
The present disclosure relates to a clock distribution device, and a signal processing device and an image display apparatus including the same. The clock distribution device according to an embodiment of the present disclosure includes: a latch configured to receive a first pulse signal among the first pulse signal and a second pulse signal having non-overlapping high levels; and a flip-flop configured to receive an inverted signal in which the second pulse signal is inverted, wherein an output clock signal is output based on an output signal of the latch, an input clock signal, and an output signal of the flip-flop. Accordingly, the input clock signal may be simply distributed.