Clock-Free EOP Detection Circuit for USB2.0 Disconnect Sensing
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Solution Overview
Problem
Existing USB2.0 repeaters face challenges in accurately detecting high-speed disconnects without a clock, as prior art circuits using Clock and Data Recovery (CDR) are expensive in terms of area and power, and clock-based methods fail to meet timing requirements for reliable detection of long End of Packet (EOP) signals in USB high-speed mode.
Innovation Solution
A clock-free analog solution involving a reset pulse generator, analog counter, and EOP detector circuit, which uses a resistor-capacitor (RC) circuit and differential-to-single-ended converter to detect the End of Packet (EOP) signal and disconnect conditions by monitoring voltage thresholds and signal reflections, eliminating the need for an accurate clock or synchronizing scheme.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If Clock and Data Recovery (CDR) circuits are used for disconnect detection, then detection accuracy is improved, but area and power consumption increase significantly
Solution Approach 1:
The patent extracts the essential function of disconnect detection from the complex CDR circuit by using only the squelch detector output and analog counter to measure packet duration, eliminating the need for full clock and data recovery functionality while maintaining detection accuracy
Solution Approach 2:
The patent replaces expensive, complex CDR circuits with simpler, lower-cost components including a squelch detector, analog counter, and threshold comparator that can accurately detect disconnects without requiring full clock recovery functionality
2Measurement precision
If Clock and Data Recovery (CDR) circuits are used for disconnect detection, then detection accuracy is improved, but power consumption increases
Solution Approach 1:
The patent extracts only the necessary timing measurement function from the CDR circuit, using the squelch detector and analog counter to measure packet duration without implementing full clock and data recovery, thereby significantly reducing power consumption
Solution Approach 2:
The patent replaces power-hungry CDR circuits with low-power components including a squelch detector, analog counter, and threshold comparator that consume significantly less power while maintaining disconnect detection accuracy
3Measurement precision
If clock-based methods are used for EOP detection, then timing synchronization is improved, but the system fails to meet timing requirements for long EOP signals
Solution Approach 1:
The patent replaces clock-based electronic timing synchronization with an analog measurement system using an RC circuit and voltage comparator that directly measures packet duration in the time domain, eliminating clock synchronization issues and meeting timing requirements for long EOP signals
Solution Approach 2:
The patent changes the timing measurement approach from frequency-domain clock synchronization to time-domain analog voltage measurement, where the analog counter output voltage directly represents packet duration and can be compared against threshold values to detect EOP conditions reliably
4Measurement precision
If a clock-based synchronizing scheme is used, then timing accuracy is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent extracts the essential timing measurement function from complex clock-based synchronizing schemes by using an analog counter that directly measures packet duration through voltage accumulation, eliminating the need for clocks, phase-locked loops, and other synchronization components
Solution Approach 2:
The patent replaces mechanical/electronic clock-based timing synchronization with an analog voltage-based time measurement system where the analog counter's output voltage directly proportional to packet duration, providing timing accuracy without synchronization complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces complexity and power consumption while providing reliable disconnect detection during Start of Frame (SOF) packets, ensuring accurate timing and efficient operation in USB2.0 repeaters, particularly suitable for smaller process nodes like 5 nm and below.
Implementation Method 1
the analog counter circuit includes a resistor-capacitor (RC) circuit
Implementation Method 2
the disconnect detector circuit is configured to indicate that the lines of a high speed path in a signal repeater are disconnected when the voltage on the lines approximately doubles in value
Data Source
AI summary
Various embodiments relate to an end of packet (EOP) circuit, including: a reset pulse generator circuit configured to generate a reset pulse when a input signal transitions to a new value; an analog counter circuit configured to receive a squelch signal to start the counter and to receive the reset pulse to reset the counter; and an EOP detector circuit configured to produce a signal indicative that the input signal is an EOP signal based upon an output of the analog counter circuit.