Clock-Free Serializer Circuit for Asynchronous Signal Race Control
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Solution Overview
Problem
Asynchronous signals in computer systems can cause race conditions and unpredictable behavior due to unsynchronized transitions, leading to potential errors and increased power consumption when synchronized using clock signals.
Innovation Solution
Serializer circuits that utilize asynchronous signals to block transitions and generate serialized signals without a clock signal, using latch circuits and delay circuits to ensure adequate time separation between signal transitions, reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If asynchronous signals are synchronized using clock signals, then signal transitions are synchronized and race conditions are avoided, but power consumption increases
Solution Approach 1:
The patent extracts and removes the clock signal from the synchronization process. Instead of using a global clock signal to synchronize all asynchronous signals, the invention allows signals to remain asynchronous while using handshake protocols and control signals to coordinate transitions only when necessary, thereby eliminating continuous clock-driven power consumption.
Solution Approach 2:
The system enables self-synchronization through handshake protocols where sending and receiving circuits automatically coordinate signal transitions without external clock control. The circuits monitor each other's state and autonomously manage synchronization, eliminating the need for continuous clock signal distribution and reducing power consumption.
2Use of energy by moving object
If asynchronous signals are transferred between circuit blocks, then power consumption is reduced, but race conditions and unpredictable behavior occur
Solution Approach 1:
The patent introduces control signals and handshake protocols as intermediaries between asynchronous signal sources and destinations. These intermediary control mechanisms coordinate transitions without requiring continuous clock synchronization, maintaining reliability while preserving the power benefits of asynchronous operation.
Solution Approach 2:
The system performs preliminary state checking and preparation before signal transitions occur. Control circuits assess the readiness of receiving blocks and prepare appropriate control signals in advance, ensuring that asynchronous transitions occur only when conditions are favorable, thereby preventing race conditions while maintaining low power consumption.
Data Source
AI summary
A serializer circuit for a computer system is disclosed. The serializer circuit may receive multiple asynchronous signals, and generate a particular serialized signal by blocking transitions of a particular asynchronous signal that corresponds to the particular serialized signal in response to a detection of a transition of at least one of the remaining asynchronous signals that does not include the particular asynchronous signal. The serializer circuit may also generate a different serialized signal by blocking transitions of a different asynchronous signal that corresponds to the different serialized signal in response to a detection of a transition of at least one of the remaining asynchronous signals that does not include the different asynchronous signal. A digital circuit may generate a particular output signal using the particular serialized signal, and generate a different output signal using the different serialized signal.