Clock Signal Frequency Control via Active and Total Counters

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Solution Overview

Problem

Existing electronic devices struggle to independently control the timing of frequency upscaling and downscaling, leading to inefficiencies in power management and performance optimization.

Innovation Solution

An electronic device is designed with a clock management unit, an intellectual property (IP) device, active and total counters, and a frequency controller. This configuration allows for independent control of frequency changes based on specific reference counts, enabling separate timing for frequency upscaling and downscaling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If frequency scaling is performed at predetermined intervals, then power management is simplified, but the frequency changes do not align with actual IP device utilization, reducing efficiency

Engineering Contradiction:

Improvepower management simplicityVSAvoidfrequency adjustment efficiency

Core Design Contradiction:

Ease of operationVSProductivity

Solution Approach 1:

The system uses active and total counters to monitor IP device utilization in real-time, creating a feedback mechanism that triggers frequency scaling only when utilization thresholds are met. This ensures frequency changes align with actual workload demands rather than following a predetermined schedule, resolving the contradiction between operational simplicity and adjustment efficiency.

Inventive Principle:

Principle #23Feedback

Solution Approach 2:

The frequency scaling mechanism transitions from static predetermined intervals to dynamic utilization-based triggering. The system continuously monitors active cycle counts and total cycle counts, adjusting frequency dynamically based on actual IP device utilization patterns, thereby improving efficiency while maintaining manageable complexity through automated counter-based control.

Inventive Principle:

Principle #15Dynamics

2Device complexity

If frequency upscaling and downscaling are controlled by the same timing mechanism, then device complexity is reduced, but independent optimization of up and down scaling timing is prevented

Engineering Contradiction:

Improvecontrol mechanism complexityVSAvoidfrequency timing control flexibility

Core Design Contradiction:

Device complexityVSAdaptability or versatility

Solution Approach 1:

The system segments the frequency control mechanism into separate active counter and total counter components. Each counter independently tracks different aspects of IP device utilization, enabling separate timing control for frequency upscaling (based on active counter) and downscaling (based on total counter). This segmentation provides independent optimization capability while maintaining manageable complexity through modular counter-based architecture.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS12339698B2Electronic device controlling frequency of clock signal and method of operating the electronic device

Publication Date: 2025.06.24 SAMSUNG ELECTRONICS CO LTD

AI summary

An electronic device includes a clock management unit configured to generate a clock signal, an intellectual property (IP) device configured to receive the clock signal and is configured to perform a task according to the clock signal in an active state, a first counter configured to count cycles of the clock signal while the IP device is in the active state, and is configured to generate a first count, and a frequency controller configured to control the clock management unit to change a frequency of the clock signal when the first count reaches a first reference count.