Clock Frequency Adjustment for IC Current Control
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Solution Overview
Problem
Power supplies face challenges in managing current demand from integrated circuits (ICs), as large ICs draw excessive current, leading to performance degradation and potential damage due to current lag, and producing application-dependent power supplies is costly.
Innovation Solution
The system employs clock gating by generating a gating signal based on a base clock signal and an enable signal to adjust the frequency of the clock signal for the IC, allowing the frequency to increase or decrease linearly or exponentially during a specified period, thereby controlling the current drawn by the IC.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the integrated circuit operates at full clock frequency to maintain performance, then processing speed is improved, but current draw increases excessively causing performance degradation and potential damage
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The system dynamically changes the clock frequency based on operational needs, allowing it to operate at full speed when necessary and reduce frequency when lower performance is acceptable, thereby optimizing the balance between processing speed and current consumption.
Solution Approach 2:
The patent changes the clock frequency parameter to control current draw. By adjusting this key parameter, the system can operate at different performance levels matching the actual computational requirements, preventing excessive current consumption while maintaining adequate processing speed for the given workload.
2Quantity of substance
If the clock frequency is reduced to decrease current draw, then power consumption is improved, but processing speed decreases
Solution Approach 1:
The system uses dynamics to adapt clock frequency in real-time based on workload requirements. Rather than operating at a fixed reduced frequency, the system can dynamically scale frequency up or down, ensuring optimal balance between power consumption and processing speed for varying operational conditions.
Solution Approach 2:
The patent employs periodic action through clock gating techniques, where the clock signal is periodically enabled or disabled based on operational requirements. This allows the system to reduce average current consumption by eliminating unnecessary clock cycles while maintaining full processing speed when actually needed.
3Quantity of substance
If a custom power supply is designed to handle high current demand, then current supply capability is improved, but manufacturing cost increases
Solution Approach 1:
The patent changes the operational parameters of the existing power supply by controlling clock frequency, thereby reducing peak current demands. This allows standard, off-the-shelf power supplies to be used instead of requiring expensive custom-designed high-current power supplies, significantly reducing manufacturing costs while maintaining system performance.
Solution Approach 2:
The system performs preliminary action by proactively managing clock frequency to prevent excessive current demands before they occur. By anticipating and controlling current draw through frequency management, the system avoids the need for over-engineered power supply solutions.
Data Source
AI summary
A system including a first clock module, a second clock module and an adjustment module. The first clock module is configured to generate a first clock signal having a first frequency. The second clock module is configured to, based on the first clock signal, generate a second clock signal for an integrated circuit. An amount of current drawn by the integrated circuit is based on a second frequency of the second clock signal. An adjustment module is configured to receive an enable signal indicating whether the integrated circuit is being powered ON. In response to the enable signal indicating the integrated circuit is being powered ON, the adjustment module (i) determines a predetermined frequency, and (ii) generate a control signal based on the first clock signal. The control signal adjusts the second frequency of the second clock signal to be between the predetermined frequency and the first frequency.