Clock Frequency Control Using Busy-Period Prediction in ICs
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Solution Overview
Problem
In semiconductor integrated circuits that dynamically control clock frequency, performance deterioration occurs due to delays in DFS control signals, leading to inefficient power consumption and operational delays during busy periods.
Innovation Solution
The semiconductor integrated circuit statistically predicts the duration of low-frequency operation and proactively returns the clock to high frequency before predicted delays, using a clock controller with a PLL circuit, frequency dividers, and clock gating circuits to adaptively manage clock frequencies based on activity monitoring and statistical processing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the clock frequency is dynamically controlled to reduce power consumption during non-busy periods, then power consumption is reduced, but performance deterioration occurs due to delays when returning to high frequency during busy periods
Solution Approach 1:
The patent applies preliminary action by statistically predicting the duration of non-busy periods in advance and proactively switching the clock frequency back to high frequency before the predicted delay period ends. This prevents performance deterioration by preparing the system ahead of time, ensuring that when busy periods actually start, the clock is already at the required high frequency without causing operational delays
Solution Approach 2:
The patent implements feedback by continuously monitoring actual busy period durations and using this information to update and refine the statistical prediction model. The prediction accuracy improves over time as the system learns from actual operational patterns, allowing for more precise timing of frequency transitions and better balancing of power consumption and performance
2Loss of energy
If the clock frequency is switched frequently between high and low frequencies, then power consumption is optimized, but delays occur due to the time required for frequency switching
Solution Approach 1:
The patent performs preliminary action by predicting the end of non-busy periods in advance and initiating frequency switching before the actual deadline. This ensures that frequency transitions are completed proactively, minimizing the impact of switching delays on operational performance while still maintaining power savings during non-busy periods
3Productivity
If statistical prediction is used to determine frequency switching timing, then operational efficiency is improved, but device complexity increases due to additional prediction circuits
Solution Approach 1:
The patent applies self-service by using the system's own historical operational data to train and update the statistical prediction model. The system learns from its own past behavior patterns, eliminating the need for external complex prediction mechanisms. This self-learning capability improves operational efficiency while keeping the added complexity minimal and manageable
Data Source
AI summary
According to one embodiment, there is provided a control method. The method includes controlling a frequency of a clock to a first frequency. The method includes changing the frequency of the clock from the first frequency to a second frequency lower than the first frequency. The method includes statically predicting a time for which the second frequency is to be continued. The method includes changing the frequency of the clock from the second frequency to the first frequency after the time for which the second frequency is to be continued elapses from a timing when the frequency of the clock is changed to the second frequency.