Clock Frequency Comparator for Reliable External Clock Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional clock detecting circuits using phase detectors face challenges in accurately detecting the frequency of external clocks, especially when the frequency is significantly higher or lower than the internal clock, leading to misinterpretation and stuck locking, resulting in high power consumption and low signal quality.
Innovation Solution
A clock detecting circuit comprising a first clock converting circuit, a second clock converting circuit, and a frequency comparator, which converts internal and external clocks and compares their frequencies by generating sensing voltages based on edge clocks, enabling accurate frequency comparison and optimization of power consumption and circuit performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a phase detector is used to detect phase difference between external clock and internal clock, then the phase alignment can be achieved, but the frequency detection capability is lost leading to misinterpretation and stuck locking
Solution Approach 1:
The clock detecting circuit is segmented into multiple functional modules: a phase detector for phase alignment, a frequency comparator for frequency detection, and a controller for coordinating operations. This segmentation allows each module to specialize in its function, resolving the contradiction between phase alignment reliability and frequency detection accuracy.
Solution Approach 2:
The clock detecting circuit is designed with multi-functionality to perform both phase detection and frequency comparison. The phase detector handles phase alignment while the frequency comparator simultaneously or sequentially detects frequency differences, making the system universal in handling both phase and frequency synchronization requirements.
2Device complexity
If the phase detector operates without frequency detection capability, then the circuit simplicity is maintained, but power consumption increases and signal quality decreases due to misinterpretation and stuck locking
Solution Approach 1:
The frequency comparator performs preliminary frequency detection before the phase detector attempts phase alignment. This preliminary action prevents misinterpretation and stuck locking by ensuring frequency compatibility first, thereby reducing power consumption and improving signal quality without significantly increasing overall circuit complexity.
Solution Approach 2:
A controller acts as an intermediary between the frequency comparator and phase detector, coordinating their operations. The controller manages the sequence of operations and integrates feedback from both modules, enabling the system to achieve both low power consumption and high signal quality while maintaining reasonable circuit complexity.
3Measurement precision
If frequency detection is added to the clock detecting circuit, then frequency accuracy is improved, but the circuit complexity increases
Solution Approach 1:
The clock detecting circuit is segmented into multiple functional modules: a phase detector for phase alignment, a frequency comparator for frequency detection, and a controller for coordinating operations. This segmentation allows each module to specialize in its function, resolving the contradiction between phase alignment reliability and frequency detection accuracy.
Solution Approach 2:
The clock detecting circuit is designed with multi-functionality to perform both phase detection and frequency comparison. The phase detector handles phase alignment while the frequency comparator simultaneously or sequentially detects frequency differences, making the system universal in handling both phase and frequency synchronization requirements.
Data Source
AI summary
A clock detecting circuit is provided. The clock detecting circuit includes a first clock converting circuit, a second clock converting circuit and a frequency comparator. The first clock converting circuit converts an internal clock to a first clock. The second clock converting circuit converts an external clock to a second clock. The frequency comparator generates a first edge clock in response the first clock and generates a second edge clock in response the second clock. The frequency comparator generates a first sensing voltage in response to a plurality of positive pulses of the first edge clock and generate a second sensing voltage in response to a plurality of positive pulses of the second edge clock. The frequency comparator compares the first sensing voltage and the second sensing voltage to provide a frequency comparing result between the external clock and the internal clock.