Clock Frequency Control Circuit for Digital Signal Reproduction
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Solution Overview
Problem
Existing digital signal recording and reproducing devices face inefficiencies in power saving due to suboptimal clock frequency management, particularly in processes like error correction and data transfer, leading to inadequate power reduction and increased energy consumption.
Innovation Solution
A device with a circuit that compares counter values from demodulating and error correcting processes to dynamically switch between high and low clock frequencies, optimizing the average clock frequency and extending error correcting process times to prioritize data transfers, thereby enhancing power saving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased to speed up error correction processing, then the processing speed is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the clock frequency adjustable rather than fixed. The system dynamically switches between high and low clock frequencies based on the actual error correction workload. When error correction is intensive, the high frequency is used to maintain speed; when errors are few or processing is complete, the system switches to low frequency to reduce power consumption. This dynamic adaptation resolves the contradiction between maintaining processing speed and reducing energy usage.
Solution Approach 2:
The patent changes the clock frequency parameter based on processing conditions. By monitoring error correction progress and workload, the system modifies the operating parameter (clock frequency) from high to low or vice versa. This parameter change allows the system to optimize the balance between processing speed and power consumption, directly addressing the technical contradiction.
2Use of energy by moving object
If the clock frequency is decreased to save power, then power consumption is reduced, but processing time increases
Solution Approach 1:
The system dynamically adjusts clock frequency based on real-time error correction status. When the error correction process is underway and time is critical, the system switches to high frequency to minimize processing time. When errors are corrected or the buffer is empty, it switches to low frequency to save power. This dynamic switching resolves the contradiction between power saving and processing time by making time a variable rather than a fixed constraint.
Solution Approach 2:
The system implements periodic monitoring of error correction progress and switches clock frequency based on these periodic checks. This periodic action allows the system to optimize power consumption during idle periods while maintaining responsiveness during active error correction, balancing the trade-off between power saving and processing time.
3Use of energy by moving object
If the clock frequency is switched frequently to optimize power saving, then power consumption is reduced, but system complexity increases
Solution Approach 1:
The system implements self-service by automatically monitoring its own error correction status and adjusting clock frequency without external intervention. The error correction circuit itself provides feedback about its progress and workload, triggering appropriate clock frequency changes. This self-service mechanism reduces the need for complex external control systems while achieving power optimization.
Solution Approach 2:
The patent employs feedback by having the error correction circuit monitor its own operation and provide signals to the clock frequency control mechanism. This feedback loop enables automatic adjustment of clock frequency based on actual processing needs, simplifying control complexity while maintaining effective power management through system-aware decision making.
Data Source
AI summary
A technique capable of realizing a power saving in a device for reproducing/recording digital signals by properly controlling a frequency of a clock. The device for reproducing/recording digital signals (device for reproducing an optical disk) includes: a difference comparing circuit for comparing a first parameter (demodulating block counter) updated each time a process for one correcting block is done in a demodulating circuit with a second parameter (error correcting block counter) updated each time a process of one correcting block is done in an error correcting circuit; and a circuit (clock controlling circuit etc.) for switching a frequency of a master clock (MCLK) depending on a comparison result of the difference comparing circuit. Thereby, the frequency of the clock can be switched both of when the demodulation for one correcting block is ended and when the correcting process for one correcting block is ended by using the switched master clock.