Clock Frequency Controller Using Efficiency-Based Dynamic Adjustment
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Solution Overview
Problem
Existing computer systems face inefficiencies in power management due to the use of a 'worst-case' conversion factor for setting processor clock frequencies, leading to unnecessary power wastage, especially in battery-powered devices, as they often overestimate the required frequency to account for non-useful work cycles, which can't be accurately determined.
Innovation Solution
A reactive Active Power Manager (APM) system that dynamically adjusts the clock frequency based on real-time processor efficiency data, using a clock frequency controller and efficiency determination module to ensure the processor meets performance targets while minimizing unnecessary power consumption by using a 'best-case' conversion factor adjusted according to current system conditions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a 'worst-case' conversion factor is used to convert instructions per second to clock frequency, then the processor can guarantee meeting performance targets, but power consumption increases unnecessarily
Solution Approach 1:
The patent applies dynamics by transitioning from a static worst-case conversion factor to a dynamic conversion factor that adapts to current processor efficiency conditions. The system monitors processor efficiency and adjusts the conversion factor accordingly, allowing the clock frequency to be optimized based on real-time performance characteristics rather than assuming worst-case scenarios continuously.
Solution Approach 2:
The patent implements feedback by introducing a monitoring mechanism that tracks processor efficiency and uses this information to adjust the clock frequency conversion factor. The system continuously measures actual processor performance, compares it against targets, and modifies the conversion factor based on this feedback, creating a closed-loop control system that balances performance guarantees with power efficiency.
2Reliability
If the clock frequency is increased to account for non-useful work cycles, then the processor can maintain performance targets, but voltage drain increases
Solution Approach 1:
The patent applies parameter changes by modifying the conversion factor used to translate instructions per second into clock frequency requests. Instead of using a fixed worst-case conversion factor, the system dynamically adjusts this parameter based on measured processor efficiency, allowing the clock frequency to be optimized for actual working conditions rather than assuming maximum inefficiency.
Solution Approach 2:
The system transitions from static power management assumptions to dynamic adjustment based on real-time efficiency monitoring. The clock frequency is no longer set based on fixed worst-case scenarios but adapts continuously to actual processor performance, reducing voltage drain when the processor operates more efficiently than expected.
3Device complexity
If a fixed conversion factor is used for clock frequency calculation, then the system is simple to implement, but it cannot accurately determine actual processor efficiency
Solution Approach 1:
The patent introduces feedback mechanisms that monitor actual processor efficiency and use this information to adjust the conversion factor. This feedback loop enables the system to accurately determine real processor efficiency by measuring actual performance against targets and using this data to refine future frequency calculations.
Solution Approach 2:
The patent replaces the simple mechanical calculation approach with a more sophisticated system that incorporates monitoring and adaptation. Instead of relying solely on fixed mathematical conversion, the system integrates efficiency measurement and dynamic adjustment, substituting a more complex but accurate approach for the simpler but less precise method.
Data Source
AI summary
One aspect of the disclosure provides a computer system. In one embodiment, the computer system comprises a clock generator, at least one processor, and a clock frequency controller. The clock generator is configured to provide a clock signal at a clock frequency. The at least one processor is configured to receive the clock signal and to operate at a speed dependent on the clock frequency. The clock frequency controller is configured to receive efficiency information indicating a current efficiency of the at least one processor. The clock frequency controller is further configured to receive a request from the processor for a target number of processor instructions to be handled in a particular time period. The clock frequency controller is further configured to output a frequency control signal to the clock generator for controlling the clock frequency in dependence thereon.