Dynamic Clock Frequency Crossover for Smooth DVFS Transitions
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Solution Overview
Problem
Abrupt changes in clock frequency cause undesirable disruptions and timing failures due to supply voltage undershoot or overshoot, rendering systems unusable until the voltage settles.
Innovation Solution
A frequency multiplier circuit with programmable transition controllers that control the transitioning frequency relationship between signal frequencies, using pre-multiplier, phase alignment, and frequency generator override controllers to minimize perturbations and ensure smooth frequency transitions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the clock frequency is increased quickly to improve performance, then the system response time is reduced, but the supply voltage undershoots causing timing failures
Solution Approach 1:
The system performs preliminary actions by pre-charging or pre-discharging the supply voltage before initiating frequency transitions. This anticipatory voltage adjustment ensures that the voltage is already at the appropriate level when the frequency change occurs, preventing undershoot or overshoot conditions that would cause timing failures.
Solution Approach 2:
The system dynamically adjusts the frequency transition rate based on real-time supply voltage conditions. By making the transition speed variable rather than fixed, the system can accelerate when voltage is stable and slow down or pause when voltage fluctuations are detected, thereby maintaining reliability while still achieving fast transitions when possible.
2Loss of time
If the clock frequency is decreased quickly to conserve power, then the system settling time is reduced, but the supply voltage overshoots causing timing failures
Solution Approach 1:
Before decreasing the clock frequency, the system preliminarily discharges the supply voltage to prevent overshoot. This preparatory voltage reduction ensures that when the frequency transition completes and load current decreases, the voltage is already at a safe level and will not overshoot to cause timing failures.
Solution Approach 2:
The system continuously monitors supply voltage levels and uses this feedback to control the frequency transition process. When voltage overshoot is detected or anticipated during a frequency decrease, the feedback mechanism adjusts or pauses the transition to allow voltage to stabilize, preventing timing failures while still achieving reasonably fast settling.
3Use of energy by moving object
If DVFS is used to optimize power and performance, then operating efficiency is improved, but abrupt frequency changes cause supply voltage perturbations
Solution Approach 1:
The system makes DVFS dynamic and adaptive by continuously monitoring supply voltage conditions and adjusting frequency transition parameters in real-time. This dynamic approach allows the system to achieve power optimization through DVFS while preventing voltage perturbations by slowing down or pausing transitions when voltage instability is detected.
Solution Approach 2:
The system implements feedback control in DVFS operations by monitoring supply voltage levels and using this information to regulate frequency transitions. When voltage perturbations are detected, the feedback mechanism adjusts the DVFS behavior to prevent further perturbations, thereby maintaining both power optimization benefits and voltage stability.
Data Source
AI summary
A clock generator system includes a first clock generator circuit to generate a first clock output signal having a first clock output frequency that is within a first bounded range of frequencies. The first clock generator circuit, during a transition mode, exhibits a first ramping of the first clock output signal from the first clock output frequency towards a target frequency. The system includes a second clock generator circuit to generate a second clock output signal having a second clock output frequency that is within a second bounded range of frequencies. The second clock generator circuit, during the transition mode, exhibits a second ramping of the second clock output signal from a second frequency towards the target frequency. A controller coupled to the first clock generator circuit and the second clock generator circuit selectively passes one of the first clock output signal or the second clock output signal as a system clock output signal. The controller, upon a desired change from a first system clock output frequency to the target frequency, switches from the first clock output signal to the second clock output signal at a dynamically-determined frequency crossover threshold.