Clock Frequency Excursion Detection with Single-Cycle Counters

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Solution Overview

Problem

Existing frequency excursion detection circuitry in systems like microcontrollers and microprocessors struggles to accurately detect frequency excursions within a single cycle of the clock signal, which can lead to system failures due to inaccurate clock signals.

Innovation Solution

The proposed frequency excursion circuitry includes a reference clock generator, a measured clock generator, and a count clock generator, along with reference and measurement counters, and comparison circuitry to detect frequency excursion by comparing counter values within a single cycle of the clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If existing frequency excursion detection circuitry is used, then the system can detect frequency variations, but the detection accuracy is insufficient within a single clock cycle

Engineering Contradiction:
Improvefrequency detection accuracyVSAvoiddetection response time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent divides the frequency detection process into multiple independent counter units (first counter circuitry and second counter circuitry) that simultaneously count clock cycles. Each counter is configured to count a specific number of cycles, and their outputs are compared to detect frequency excursions. This segmentation allows the system to achieve accurate single-cycle detection by comparing discrete count values rather than requiring multi-cycle averaging.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces comparison circuitry as an intermediary element that receives count values from multiple counter units and determines whether a frequency excursion has occurred. This intermediary component enables the system to make rapid frequency detection decisions by comparing discrete count values within a single clock cycle, rather than requiring continuous measurement and processing of frequency signals over multiple cycles.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Measurement precision

If multi-cycle detection is used to improve accuracy, then measurement precision increases, but the detection delay increases

Engineering Contradiction:
Improvefrequency excursion detection accuracyVSAvoiddetection time duration
Core Design Contradiction:
Measurement precisionVSDuration of action of moving object

Solution Approach 1:

The patent configures counter circuitry to pre-count a predetermined number of clock cycles simultaneously. The first counter circuitry is configured to count a first number of clock cycles and the second counter circuitry is configured to count a second number of clock cycles. By the time comparison is needed, the counting action has already been performed, enabling immediate frequency excursion detection without requiring additional measurement time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent uses periodic clock signals to drive the counter circuitry, where each clock cycle represents a discrete measurement period. The counters accumulate cycle counts over predetermined periods, and the comparison circuitry evaluates these periodic count values to detect frequency excursions. This periodic action allows the system to achieve accurate frequency measurement within a single clock cycle by leveraging the regular, predictable nature of clock-based counting.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS20250117038A1Method and apparatus for early detection of signal excursion out of frequency range
Publication Date: 2025.04.10 TEXAS INSTRUMENTS INC
  • US20250117038A1 patent drawing
  • US20250117038A1 patent drawing
  • US20250117038A1 patent drawing

AI summary

An example device comprising: first clock divider circuitry to be coupled to a first clock; first counter circuitry configured to be coupled to the first clock divider circuitry, the first counter circuitry configured to increment based on the first clock and a second clock; second clock divider circuitry to be coupled to a third clock; second counter circuitry configured to be coupled to the second clock divider circuitry, the second counter circuitry configured to increment based on the third clock and the second clock; and comparison circuitry coupled to the first and second counter circuitry.