Adaptive Clock Frequency Scaling With Hardware Gating Control
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Solution Overview
Problem
Existing solutions for reducing clock signal frequency in integrated circuits have slow response times and rely on multiple phase locked loops or integer fraction divider circuits, leading to inefficient power management and potential performance drops in fast-changing scenarios.
Innovation Solution
The implementation of adaptive frequency scaling circuitry that dynamically adjusts clock signal frequency based on operating conditions using hardware-based control, allowing for immediate response and finer granularity in frequency adjustments with a single PLL, incorporating scaling control circuitry and clock gating mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If software-based control is used to adjust clock signal frequency, then power consumption is reduced, but response time becomes slow and performance may drop in fast-changing scenarios
Solution Approach 1:
The patent replaces software-based control with a hardware-based clock frequency adjustment mechanism. The clock tree synthesis tool generates multiple clock tree implementations with different frequency scaling capabilities, and hardware control logic selectively activates them based on operating conditions. This hardware-based approach eliminates the slow response time inherent in software-based control while maintaining power consumption benefits.
2Adaptability or versatility
If multiple phase locked loops or divider circuits are used to generate clock signals with different frequencies, then frequency adjustment capability is improved, but device complexity increases
Solution Approach 1:
The patent segments the clock distribution network into multiple clock tree implementations, where each implementation is optimized for a specific frequency range or performance requirement. The clock tree synthesis tool divides the overall clock distribution task into separate clock trees that can be independently controlled and activated based on operating conditions, providing frequency adjustment capability without requiring multiple PLLs or divider circuits.
Solution Approach 2:
Each clock tree implementation serves multiple functions: it can operate at different frequency scales, serve different functional blocks, and be activated based on various operating conditions. This multi-functionality allows a single clock tree implementation to replace what would traditionally require multiple specialized circuits, thereby reducing overall device complexity.
Data Source
AI summary
Systems, methods, and circuitries are disclosed generating a dynamic clock signal having a dynamic clock signal frequency for a data processing system from an input clock signal having an input clock signal frequency. In one example, adaptive frequency scaling circuitry includes scaling control circuitry and clock gating circuitry. The scaling control circuitry includes hardware configured to receive a performance indicator value indicative of an operating parameter of the data processing system and select a dynamic clock gating control value based at least on the performance indicator value. The clock gating circuitry is configured to receive the dynamic clock gating control value, and in response, selectively gate the input clock signal based on the dynamic clock gating control value to generate the dynamic clock signal.