Clock Signal Frequency Management for Wireless Interference Avoidance

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Solution Overview

Problem

In electronic devices, clock signal frequencies often interfere with other signals, particularly in wireless communications, leading to performance degradation and interference issues due to coincident frequencies and harmonics.

Innovation Solution

The frequency of a clock signal is dynamically changed to avoid interference by selecting a new frequency that is not coincident with other signals, using a clock control unit and phase locked loop (PLL) circuitry, with the help of a list of safe and non-safe frequencies generated based on pending frequency changes in wireless communications, and employing a glitch-free multiplexer to manage the frequency change.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the frequency of a clock signal is fixed to maintain stable operation, then reliability is improved, but interference with other signals (particularly wireless communications) occurs due to coincident frequencies and harmonics

Engineering Contradiction:
Improvestable operationVSAvoidinterference with other signals
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies dynamics by making the clock signal frequency adjustable rather than fixed. The system dynamically changes the clock frequency based on the operational state of wireless communications interfaces, selecting from multiple available frequencies to avoid interference while maintaining stable data transmission operation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the frequency parameter of the clock signal to resolve interference issues. By modifying the clock frequency parameter to values that do not coincide with wireless communication frequencies or their harmonics, the system eliminates interference while preserving reliable data transmission.

Inventive Principle:
Principle #35Parameter changes

2Object-affected harmful factors

If the frequency of the clock signal is dynamically changed to avoid interference, then harmful factors are reduced, but device complexity increases due to additional control circuitry and frequency management

Engineering Contradiction:
Improveinterference reductionVSAvoidcontrol circuitry and frequency management
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The patent merges the clock control functionality with the existing data transmission interface control. The same control unit that manages data transmission also controls the clock frequency, eliminating the need for separate dedicated frequency management circuitry and reducing overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The control unit is designed to perform multiple functions: managing data transmission and simultaneously controlling clock frequency selection. This multi-functional approach reduces the need for separate dedicated circuits for frequency management, thereby reducing device complexity while maintaining interference avoidance capabilities.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Adaptability or versatility

If frequency changes are implemented rapidly to avoid interference, then adaptability is improved, but spurious activity and signal instability occur during transitions

Engineering Contradiction:
Improvefrequency adaptationVSAvoidspurious activity during transitions
Core Design Contradiction:
Adaptability or versatilityVSObject-generated harmful factors

Solution Approach 1:

The system performs preliminary actions by preparing the new clock frequency in advance before actually switching to it. The control unit selects and prepares the target frequency based on predicted wireless communication frequency changes, ensuring a smooth transition that minimizes spurious activity and maintains signal stability.

Inventive Principle:
Principle #10Preliminary action

4Object-affected harmful factors

If the clock frequency is changed to avoid interference with wireless signals, then harmful factors are reduced, but loss of time occurs during frequency transition

Engineering Contradiction:
Improveinterference avoidanceVSAvoidfrequency transition time
Core Design Contradiction:
Object-affected harmful factorsVSLoss of time

Solution Approach 1:

The system rushes through the frequency transition process by implementing rapid frequency switching mechanisms. The control unit quickly changes the clock frequency when interference is detected, minimizing the duration of the transition and reducing the time loss, while ensuring the transition completes before affecting data transmission integrity.

Inventive Principle:
Principle #21Skipping (Rushing through)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces or eliminates interference between clock signals and wireless communications signals, ensuring seamless operation and minimizing spurious activity during frequency changes, thereby enhancing performance and reducing interference.

Implementation Method 1

using a clock control unit and phase locked loop (PLL) circuitry

Methodology Applied
Scientific EffectPhase locked loop:

Data Source

PatentUS8644782B2Agile clocking with receiver PLL management
Publication Date: 2014.02.04 APPLE INC
  • US8644782B2 patent drawing
  • US8644782B2 patent drawing
  • US8644782B2 patent drawing

AI summary

A method and apparatus for changing a frequency of a clock signal to avoid interference is disclosed. In one embodiment, data conveyed on a first interface is synchronized to a clock signal at a first frequency. Signals are conveyed on a second interface at another frequency. Responsive to a change of the frequency at which signals are conveyed on a second interface, a clock control unit associated with the first interface initiates a change of the clock signal to a second frequency. The second frequency may be chosen as to not cause interference with the frequency at which signals are conveyed on the second interface. The change of the clock frequency may be performed in such a manner as to prevent spurious activity on the clock line of the interface.