Clock Frequency Estimation Using Least Squares Sampling
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Solution Overview
Problem
Existing clock frequency estimation methods suffer from high estimation errors due to measurement noise and require complex circuitry or significant processor time, with error reduction proportional to 1/N^2, and simpler methods introduce large errors.
Innovation Solution
The use of a least squares method for clock frequency estimation, involving time measurements at rising edges, reduces estimation error to 1/N^3 by employing a sampling circuit and estimation circuit with accumulators and multipliers to calculate the clock period accurately.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If brute-force calculation of average clock period is used, then measurement precision is improved with error reduction proportional to 1/N^2, but device complexity increases requiring large and complex circuitry or significant processor time
Solution Approach 1:
The patent changes the computational approach from brute-force average calculation to least squares estimation, transforming the mathematical parameters used in the calculation. This allows achieving higher measurement precision (error reduction proportional to 1/N^3 instead of 1/N^2) while maintaining comparable circuit complexity by using a different estimation framework that can be implemented with similar hardware resources.
2Device complexity
If simpler cycle-by-cycle frequency calculation is used, then device complexity is reduced, but measurement precision deteriorates with large estimation errors
Solution Approach 1:
The patent introduces an intermediary least squares estimation process between the simple cycle-by-cycle measurement and the final frequency calculation. This intermediary step processes the raw time measurements through a least squares algorithm, achieving error reduction proportional to 1/N^3 while keeping the overall system complexity manageable through efficient implementation of the estimation algorithm.
Data Source
AI summary
An apparatus includes a clock signal input, a sampling circuit, and an estimation circuit. The clock signal input receives N time measurements. A time measurement denotes a respective portion of a given cycle of a clock signal. The sampling circuit is to generate a first sampled window from the clock signal input. The first sampled window includes an accumulation of the N time measurements. The sampling circuit is to generate a second sampled window from the clock signal input including an accumulation of a plurality of products. The estimation circuit is to estimate the frequency or period of the clock signal based upon the first sampled window and the second sampled window.