Circuit Test System Clock Frequency Multiplication for High-Speed Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional high-speed electronic circuit testing methods require expensive testers and do not adequately test critical components like clock receivers, FIFO buffers, and clock trees, necessitating a cost-effective solution for high-speed testing.
Innovation Solution
A circuit test system and method that utilizes a first and second test loop within the circuit to be tested, driven by a clock signal whose frequency is multiplied, allowing for high-speed testing without the need for a high-speed tester, by forming loops between input/output pads and using clock generation units to provide read and write clocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a high speed tester is used to test electronic circuits at high speed, then testing speed and performance are improved, but testing cost increases significantly
Solution Approach 1:
The circuit under test generates its own high-frequency clock signals through internal frequency multiplication circuits, eliminating the need for external high-speed test equipment. The device serves itself by using its own resources (power, logic circuits, frequency multipliers) to create the test conditions required for high-speed operation verification.
Solution Approach 2:
The test system uses a single low-frequency clock signal source that can be frequency-multiplied to generate multiple different high-frequency clock signals for testing various functions simultaneously. The same basic infrastructure (clock generator, frequency multipliers) serves multiple testing purposes including clock receiver testing, FIFO buffer testing, and data path testing at different speeds.
2Ease of manufacture
If conventional test methods are used, then testing cost is reduced, but testing coverage is insufficient as critical components like clock receivers, FIFO buffers, and clock trees are not tested
Solution Approach 1:
The testing process is divided into separate test modes that can be independently activated: first test mode for clock receiver and first FIFO buffer, second test mode for additional FIFO buffers and clock trees. This segmentation allows comprehensive coverage of all critical components while using the same cost-effective test infrastructure.
Solution Approach 2:
The system dynamically configures different test loops and activates different frequency multiplication circuits based on the selected test mode. The clock generation units can be selectively enabled to provide appropriate clock frequencies for different testing scenarios, allowing the system to adapt its behavior to achieve comprehensive coverage without requiring multiple static test setups.
3Speed
If frequency multiplication is used to generate high-speed clock signals, then high-speed testing capability is achieved, but circuit complexity increases
Solution Approach 1:
Multiple frequency multiplication circuits are integrated within the single device under test, allowing them to share common infrastructure such as power supply, control logic, and output buffers. The clock generation units are merged into the device's existing logic fabric, utilizing available resources rather than adding completely separate external frequency synthesis systems.
Data Source
AI summary
A circuit test system including a circuit test apparatus and a circuit to be tested is provided. The circuit test apparatus provides a first clock signal. The circuit to be tested includes a plurality of input/output pads and at least one clock pad. At least two input/output pads of the input/output pads are connected to each other to form a test loop during a test mode. The clock pad receives the first clock signal. The circuit to be tested multiplies a frequency of the first clock signal to generate a second clock signal, and the test loop of the circuit to be tested is tested based on the second clock signal during the test mode. The frequency of the second clock signal is higher than that of the first clock signal. Furthermore, a circuit test method of the foregoing circuit test system is also provided.