Clock Frequency Conversion Circuit With Phase-Aligned Switching
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Solution Overview
Problem
Semiconductor apparatuses with high operation speeds face increased power consumption and require circuits to convert high-frequency clocks to low-frequency clocks without introducing phase differences, necessitating a solution for adaptive frequency control.
Innovation Solution
A semiconductor apparatus with a multiplication control block generating frequency control signals and a clock output block that adjust the input clock frequency based on a multiplication determination signal, enabling synchronization reset and asynchronization reset signals to initialize and fix these signals, ensuring no phase difference during frequency conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation speed of a semiconductor apparatus is increased, then the processing capability is improved, but the power consumption markedly increases
Solution Approach 1:
The patent implements dynamic frequency adjustment by providing a frequency control signal that can vary the operating frequency of the semiconductor apparatus. The apparatus can switch between different frequency states (first frequency and second frequency) based on operational requirements, allowing the system to adapt its performance characteristics in real-time rather than operating at a fixed high frequency.
2Use of energy by moving object
If frequency conversion is performed to reduce power consumption, then the operation speed can be reduced, but phase difference may occur between clocks before and after conversion
Solution Approach 1:
The patent introduces a phase adjustment circuit as an intermediary component between the frequency conversion elements. This phase adjustment circuit specifically compensates for phase differences introduced during frequency conversion by adjusting the phase of the clock signal. The circuit includes phase adjustment units that can independently control the phase of each clock signal to ensure synchronization between the original and converted clocks.
3Use of energy by moving object
If the operation speed is reduced to decrease power consumption, then the processing capability decreases, but the apparatus needs to maintain both high speed and low speed operation capabilities
Solution Approach 1:
The patent designs a frequency control system that provides multiple frequency states (first frequency for high-speed operation and second frequency for low-speed operation). The system can selectively operate at different frequencies based on the specific task requirements, making the semiconductor apparatus universally capable of handling both performance-critical and power-efficient operational scenarios.
4Adaptability or versatility
If a circuit for converting clock frequency is added, then both high speed and low speed operation become possible, but the device complexity increases
Solution Approach 1:
The frequency control system is segmented into distinct functional blocks: a frequency control unit that generates control signals, a phase adjustment circuit that compensates for phase differences, and clock output units that provide the final clock signals. This segmentation allows each component to be optimized independently and facilitates modular design and implementation.
Data Source
AI summary
A semiconductor apparatus includes a multiplication control block configured to generate a plurality of frequency control signals according to an input clock and a multiplication determination signal; and a clock output block configured to generate an output clock according to the input clock, the multiplication determination signal and the plurality of frequency control signals.