Clock Frequency Detection for Pin-Free PLL Startup Configuration
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Solution Overview
Problem
Current integrated circuits face challenges in providing flexible clock frequency configurations without additional pins, leading to increased development costs and potential PLL malfunctions due to complex pin configurations.
Innovation Solution
An Automatic System-Clock Detection System (ASCDS) that uses an internal ring oscillator and watchdog counter to detect the frequency of an external periodic signal and adjust the internal PLL, eliminating the need for extra pins by determining the clock frequency at startup.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If additional pins are added to the IC for clock frequency configuration, then clock frequency flexibility is improved, but device complexity and development cost increase
Solution Approach 1:
The IC performs self-detection of the external clock frequency using an internal ring oscillator and frequency detection circuitry. The system automatically determines the clock frequency without requiring external configuration pins, allowing the device to self-configure based on detected parameters. This eliminates the need for additional configuration pins while maintaining adaptability to different clock frequencies.
Solution Approach 2:
The system changes its operational parameters by detecting the external clock frequency and automatically adjusting the PLL configuration accordingly. Instead of requiring fixed configuration pins, the system dynamically adapts its parameters (PLL multiplication factors, division ratios) based on the detected clock frequency, enabling flexible operation across multiple frequency ranges.
2Adaptability or versatility
If additional pins are added to the IC for clock frequency configuration, then clock frequency flexibility is improved, but manufacturing cost increases
Solution Approach 1:
The IC performs self-detection of the external clock frequency using an internal ring oscillator and frequency detection circuitry. The system automatically determines the clock frequency without requiring external configuration pins, allowing the device to self-configure based on detected parameters. This eliminates the need for additional configuration pins while maintaining adaptability to different clock frequencies.
Solution Approach 2:
The existing input pins are designed to serve multiple functions: they can accept external clock signals across different frequency ranges without requiring separate dedicated pins for each frequency configuration. The system universally handles various clock frequencies through software-based detection and configuration, making the hardware design more manufacturable and cost-effective.
3Adaptability or versatility
If complex pin configurations are required for clock frequency selection, then clock frequency flexibility is improved, but reliability decreases due to potential configuration errors
Solution Approach 1:
The IC performs self-detection of the external clock frequency using an internal ring oscillator and frequency detection circuitry. The system automatically determines the clock frequency without requiring external configuration pins, allowing the device to self-configure based on detected parameters. This eliminates the need for additional configuration pins while maintaining adaptability to different clock frequencies.
Solution Approach 2:
The system implements a feedback mechanism where the detected clock frequency is used to automatically configure the PLL parameters. The frequency detection circuitry provides feedback about the external clock characteristics, and this information is used to adjust the PLL multiplication and division factors, ensuring reliable operation across different frequency ranges without manual configuration errors.
4Adaptability or versatility
If multiple clock select pins are used for frequency configuration, then clock frequency flexibility is improved, but ease of operation decreases
Solution Approach 1:
The IC performs self-detection of the external clock frequency using an internal ring oscillator and frequency detection circuitry. The system automatically determines the clock frequency without requiring external configuration pins, allowing the device to self-configure based on detected parameters. This eliminates the need for additional configuration pins while maintaining adaptability to different clock frequencies.
Solution Approach 2:
The system performs preliminary frequency detection and PLL configuration automatically at startup before any operational commands are issued. The frequency detection circuitry is activated first to determine the external clock characteristics, and based on this preliminary detection, the PLL parameters are pre-configured, simplifying the startup process and eliminating the need for manual pin configuration by the user.
Data Source
AI summary
An Automatic System Clock Detection System (ASCDS) may provide integrated circuits (ICs) with the capability to detect the frequency of an external crystal oscillator or clock source, and adjust the IC's internal PLL accordingly for proper IC operation. The frequency detection and PLL adjustment may be performed without any additional pins on the IC, and/or without requiring any additional external information. The ASCDS may be configured with an internal ring oscillator, which may be generated from standard logic elements, a watchdog counter, and an input clock counter. When the IC comes out of power on reset (POR), the ASCDS may compare the input clock counter with the watchdog counter, and determine the clock frequency of the input clock. It may then set the PLL parameters to ensure correct IC operation.