Clock Branch Frequency Ramp-Up to Prevent Voltage Drop
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Solution Overview
Problem
Conventional clock generation systems face issues with sudden voltage drops due to high loading and increasing operation frequency, leading to false circuit actions.
Innovation Solution
A clock generation system with a time and frequency division activation mechanism, featuring a clock source processing circuit and multiple clock-branching circuits that gradually decrease the divisor number over time to increase the branch frequency of clock signals, preventing sudden voltage drops by controlling the output of branch clock signals through a frequency division unit and processing unit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the operation frequency is increased and the number of loadings is increased, then the performance and functionality of the clock system is improved, but the voltage drops suddenly causing false circuit action
Solution Approach 1:
The patent applies preliminary action by gradually increasing the operation frequency in stages before reaching the final target frequency. The clock generation system uses a frequency division unit that divides the clock signal by a divisor number that is gradually decreased from an initial value to a final value, allowing the system to prepare for high-frequency operation incrementally rather than suddenly, thus preventing voltage drops and false circuit actions.
2Speed
If the divisor number is decreased to increase branch frequency, then the clock signal frequency is improved, but sudden voltage drops occur
Solution Approach 1:
The patent applies dynamics by making the divisor number a dynamic parameter that changes gradually over time rather than remaining fixed or changing abruptly. The processing unit controls the frequency division unit to adjust the divisor number from an initial divisor number larger than one to a final divisor number in a controlled manner, allowing the branch frequency to increase dynamically while preventing harmful voltage drops.
3Adaptability or versatility
If the clock tree branches to transmit clock signals to multiple circuit blocks, then the system coverage is improved, but the chip size becomes larger and voltage drops increase
Solution Approach 1:
The patent applies segmentation by dividing the clock distribution system into multiple clock-branching circuits, each with its own frequency division unit and processing unit. Each clock-branching circuit independently manages a portion of the clock distribution, allowing the system to cover multiple circuit blocks while reducing the overall chip size compared to a single centralized clock tree.
Data Source
AI summary
A clock generation system having a time and frequency division activation mechanism is provided that includes a clock source processing circuit that generates a primary clock signal and clock-branching circuits that perform a clock-branching generation procedure respectively in an order. Each of the clock-branching modules includes a frequency division unit and a processing unit. The frequency division unit receives the primary clock signal to divide the frequency according to a divisor number and output a branch clock signal. The processing unit controls the frequency division unit to not output the branch clock signal before the clock-branching generation procedure and to decrease the divisor number gradually over time period after the clock-branching generation procedure begins such that a branch frequency of the branch clock signal generated by the frequency division unit increases from an initial frequency to a final frequency to finish the clock-branching generation procedure.