Clock Frequency Ratio Estimation Using Cycle Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for determining the clock relationship between high and low frequency clocks in mobile devices are inefficient, leading to potential synchronization loss and increased standby time, as they require complex scheduling and lengthy frequency ratio estimation processes.
Innovation Solution
A data processing device that generates both high and low frequency clock signals, samples the high frequency clock at times determined by the low frequency clock, and calculates the frequency relationship by minimizing deviations in clock cycle numbers, allowing for rapid and accurate clock frequency ratio estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If complex scheduling and lengthy frequency ratio estimation processes are used to determine clock relationship, then measurement precision is improved, but loss of time increases and productivity decreases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing frequency ratio estimates in a lookup table during device manufacturing or initialization. When determining clock relationship during operation, the system directly queries this pre-computed table rather than performing lengthy real-time estimation, thus achieving accurate clock relationship determination without time-consuming calculations during active operation
Solution Approach 2:
The patent implements dynamics by adapting the frequency ratio estimation approach based on operational context. The system uses a simplified dynamic estimation method that leverages previously stored frequency ratios and makes minimal adjustments based on current clock cycle measurements, rather than always performing complete static frequency ratio estimation, thereby reducing computation time while maintaining sufficient accuracy
2Measurement precision
If complex scheduling and lengthy frequency ratio estimation processes are used to determine clock relationship, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent eliminates complex runtime scheduling by pre-computing frequency ratios and storing them in lookup tables during device initialization. This preliminary action transfers the computational burden from runtime operation to setup phase, allowing the device to determine clock relationships through simple table queries without requiring complex scheduling algorithms or coordination during active operation
Solution Approach 2:
The patent replaces complex mechanical/computational frequency estimation mechanisms with a simplified lookup-based system. Instead of implementing intricate frequency measurement and calculation hardware or software routines during operation, the system substitutes these with pre-computed data tables and simple comparison logic, significantly reducing device complexity while maintaining measurement precision
3Reliability
If high frequency clock is continuously enabled for accurate synchronization, then reliability is improved, but use of energy increases
Solution Approach 1:
The patent implements periodic action by enabling the high-frequency clock only during specific wake-up intervals when synchronization checks are performed, rather than keeping it continuously enabled. The low-frequency clock maintains basic timing functions during sleep mode, and the high-frequency clock is activated periodically to perform quick synchronization verification using the pre-stored frequency ratios, thereby maintaining reliability while dramatically reducing average power consumption
Solution Approach 2:
The patent applies preliminary action by pre-calculating and storing frequency ratio relationships during initialization, enabling the system to perform rapid synchronization checks when the high-frequency clock is briefly activated. This preliminary preparation allows the high-frequency clock to be disabled for extended periods, reducing power consumption while maintaining synchronization accuracy through efficient periodic verification using stored reference data
Data Source
AI summary
A data processing device is described comprising a first clock generator configured to generate a first clock signal with a first frequency; a second clock generator configured to generate a second clock signal with a second frequency, wherein the second frequency is higher than the first frequency; and a processing circuit configured to sample a clock cycle number of the second clock signal at a plurality of sample times given by the first clock signal and determine a relationship between the first frequency and the second frequency based on a minimization of a measure of a deviation of the sampled clock cycle numbers from the clock cycle numbers of the second clock signal at the plurality of sample times expected according to the determined relationship.