Clock Signal Frequency Transition for Stable Receiver Lock

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Solution Overview

Problem

Conventional clock signal generation at the receiving end fails to swiftly track frequency variations from the transmitting end, leading to unstable clock signals and abnormal operations, such as picture flicker in TV displays, due to hardware limitations, necessitating the termination of transmission processes.

Innovation Solution

A signal transmission system with a first clock signal generator that enters a frequency-unlocked state during a first time period and a second clock signal generator that maintains a frequency-locked state by controlling the frequency transition of the clock signal from the transmitting end, allowing the receiving end to smoothly adjust to new frequencies without terminating the transmission process.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the clock signal frequency at the transmitting end changes significantly within a short time period, then the frequency transition speed is improved, but the receiving end clock generator cannot track the frequency variation swiftly, leading to unstable clock signals and abnormal operations

Engineering Contradiction:
Improvefrequency transition speedVSAvoidclock signal stability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The patent applies dynamics by making the clock signal frequency transition gradual rather than abrupt. The transmitting end clock generator dynamically adjusts the frequency over an extended period, allowing the receiving end to track the frequency variation smoothly. This dynamic approach resolves the contradiction by enabling both fast frequency transition and stable clock signal generation simultaneously.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements preliminary action by extending the frequency transition period at the transmitting end before the receiving end completes its frequency acquisition. This preliminary frequency adjustment allows the receiving end clock generator to lock onto the new frequency without instability, preventing abnormal operations while maintaining efficient frequency transitions.

Inventive Principle:
Principle #10Preliminary action

2Reliability

If the transmission process is terminated to allow the clock generator at the receiving end to lock to a new frequency, then the clock signal stability is improved, but the productivity is reduced due to interruption of data transmission

Engineering Contradiction:
Improveclock signal stabilityVSAvoiddata transmission continuity
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent applies continuity of useful action by maintaining data transmission throughout the frequency transition process. The transmitting end extends the frequency transition period and the receiving end extends its frequency acquisition period, allowing both operations to complete successfully without interrupting data transmission. This resolves the contradiction by achieving both clock signal stability and continuous productivity.

Inventive Principle:
Principle #20Continuity of useful action

Solution Approach 2:

The patent implements preliminary action by preparing the clock frequency transition in advance with extended time periods, allowing the receiving end to acquire the new frequency without stopping data transmission. This preliminary preparation enables continuous productivity while maintaining reliability.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If the clock generator at the receiving end uses hardware with limited frequency tracking capability, then the device complexity is reduced, but the adaptability is worsened when frequency changes are significant

Engineering Contradiction:
Improveclock generator hardware complexityVSAvoidfrequency tracking capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The patent applies parameter changes by modifying the time period parameters of the frequency transition process. The transmitting end extends the frequency transition period, and the receiving end extends its frequency acquisition period. This parameter adjustment allows simple hardware to achieve better frequency tracking adaptability without increasing device complexity.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent applies dynamics by making the frequency transition process adaptive to the hardware capabilities. By extending the transition and acquisition periods, the system dynamically adjusts to accommodate limited frequency tracking capability while maintaining overall system adaptability for significant frequency changes.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS8619932B2Signal transmission system with clock signal generator configured for generating clock signal having stepwise/smooth frequency transition and related signal transmission method thereof
Publication Date: 2013.12.31 INTERLINK SILICON SOLUTIONS INC
  • US8619932B2 patent drawing
  • US8619932B2 patent drawing
  • US8619932B2 patent drawing

AI summary

A signal transmission system includes a first clock signal generator and a second clock signal generator. The first clock signal generator is configured for generating a first clock signal according to clock information derived from a transmitted signal, wherein the transmitted signal is changed in response to a frequency change of a second clock signal, and the first clock signal generator enters a frequency-unlocked state if the second clock signal has a frequency transition from a first frequency to a second frequency during a first time period. The second clock signal generator is configured for generating the second clock signal having the frequency transition from the first frequency to the second frequency during a second time period longer than the first time period such that the first clock signal generator stays in a frequency-locked state during the second time period.