Clock Frequency Shifter Using Sawtooth Delay for Spectral Purity
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Solution Overview
Problem
Conventional clock signal generation and distribution methods face challenges such as high power consumption, high manufacturing costs, and crosstalk issues due to the use of multiple phase-locked loops (PLLs) for generating multiple clock signals with precise frequencies, which also lead to injection-locking problems and spectral impurities.
Innovation Solution
The implementation of a frequency shifter system that includes an M-to-1 multiplexer, a fractional frequency divider, and a tunable delay element controlled by a sawtooth signal, which reduces timing errors and improves spectral purity by adjusting the phase of the clock signal, allowing for efficient generation and distribution of multiple clock signals with arbitrary frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple PLLs are used to generate multiple clock signals with precise frequencies, then frequency precision is improved, but power consumption increases and manufacturing cost increases
Solution Approach 1:
The patent combines multiple PLL functions into a single PLL by using a frequency divider with programmable division ratios. Instead of employing multiple independent PLLs to generate different clock frequencies, the system uses one PLL whose output is divided by different integer factors to produce multiple clock signals, thereby reducing power consumption and component count while maintaining frequency precision.
Solution Approach 2:
The frequency divider is designed to be universal, capable of providing different division ratios (N1, N2, N3, etc.) to generate multiple clock frequencies from a single PLL output. This multi-functional approach eliminates the need for dedicated PLLs for each frequency, reducing overall system power consumption and manufacturing cost.
2Measurement precision
If multiple PLLs are used to generate multiple clock signals with precise frequencies, then frequency precision is improved, but manufacturing cost increases
Solution Approach 1:
The patent merges multiple PLL circuits into a single PLL implementation, significantly reducing the number of critical components (VCOs, loop filters, dividers) that need to be manufactured and assembled. This consolidation directly lowers manufacturing cost while maintaining the ability to generate multiple precise clock frequencies through programmable division ratios.
Solution Approach 2:
Instead of manufacturing multiple identical PLL circuits, the system creates logical copies of the frequency division function through software-programmable dividers. This allows the same hardware PLL to serve multiple frequency generation purposes, reducing manufacturing complexity and cost.
3Measurement precision
If multiple PLLs are placed in close proximity to generate clock signals, then frequency precision is maintained, but crosstalk and magnetic coupling increase
Solution Approach 1:
By consolidating multiple PLL functions into a single physical PLL unit, the patent eliminates the spatial proximity issue that causes crosstalk and magnetic coupling. With only one oscillator and one set of loop filter components, there are no adjacent high-frequency signals to interfere with each other, while frequency precision is maintained through programmable frequency division.
4Measurement precision
If multiple PLLs are placed in close proximity to generate clock signals, then frequency precision is maintained, but injection-locking risk increases
Solution Approach 1:
The patent eliminates injection-locking risk by using a single PLL instead of multiple PLLs in close proximity. Since there is only one oscillator generating the reference frequency, there are no other oscillators that could inadvertently lock to each other's frequencies. The system maintains frequency precision through digital frequency division rather than through multiple analog oscillators.
5Adaptability or versatility
If a fractional-N divider is used in the feedback path of a PLL for fractional frequency multiplication, then frequency flexibility is improved, but spectral purity deteriorates due to large fractional spurs
Solution Approach 1:
The patent segments the frequency multiplication function into two separate stages: first, an integer-N PLL provides a clean fundamental frequency with excellent spectral purity; second, a frequency divider with programmable division ratios provides the fractional frequency multiplication. This segmentation allows the system to achieve frequency flexibility through digital division while maintaining spectral purity by keeping the analog PLL section simple and clean.
Solution Approach 2:
The patent introduces an intermediary frequency divider stage between the PLL output and the final clock outputs. This intermediary component acts as a buffer that converts the clean PLL output into multiple fractional frequency signals without introducing the spectral impurities that would result from using a fractional-N divider directly in the PLL feedback path.
Data Source
AI summary
A “frequency shifter” is a clock synthesis system, that includes either a multiplexer or a multi-modulus divider (MMD), a fractional frequency divider, a tunable delay element, a sawtooth signal generator, in addition to other synchronization and control circuits. The generated sawtooth signal is used to control the delay of the tunable delay element, which in turn is used to adjust the phase of the signal generated by either M-to-1 multiplexer or the MMD, reducing its timing errors, and improving the spectral purity of the generated clock signal.